Packet : 43680548rd1010_source_code.zip filelist
sdram_controller_xm/
sdram_controller_xm/docs/
sdram_controller_xm/docs/filelist.txt
sdram_controller_xm/docs/readme.txt
sdram_controller_xm/docs/user's guide.doc
sdram_controller_xm/par/
sdram_controller_xm/par/xm/
sdram_controller_xm/par/xm/sdr_top.log
sdram_controller_xm/par/xm/sdr_top.mrp
sdram_controller_xm/par/xm/sdr_top.pad
sdram_controller_xm/par/xm/sdr_top.par
sdram_controller_xm/par/xm/sdr_top.prf
sdram_controller_xm/par/xm/sdr_top.sdf
sdram_controller_xm/par/xm/sdr_top.tcl
sdram_controller_xm/par/xm/sdr_top.vo
sdram_controller_xm/par/xm/sdr_top_overconstraint.twr
sdram_controller_xm/par/xm/sdr_top_post.prf
sdram_controller_xm/par/xm/sdr_top_post_route_trace.twr
sdram_controller_xm/simulation/
sdram_controller_xm/simulation/readme.txt
sdram_controller_xm/simulation/xm/
sdram_controller_xm/simulation/xm/modelsim/
sdram_controller_xm/simulation/xm/modelsim/rtl/
sdram_controller_xm/simulation/xm/modelsim/rtl/rtl_sim.log
sdram_controller_xm/simulation/xm/modelsim/scripts/
sdram_controller_xm/simulation/xm/modelsim/scripts/sdr_fsim.tcl
sdram_controller_xm/simulation/xm/modelsim/scripts/sdr_tsim.tcl
sdram_controller_xm/simulation/xm/modelsim/timing/
sdram_controller_xm/simulation/xm/modelsim/timing/timing_sim.log
sdram_controller_xm/source/
sdram_controller_xm/source/sdr_ctrl.v
sdram_controller_xm/source/sdr_data.v
sdram_controller_xm/source/sdr_par.v
sdram_controller_xm/source/sdr_sig.v
sdram_controller_xm/source/sdr_top.v
sdram_controller_xm/synthesis/
sdram_controller_xm/synthesis/xm/
sdram_controller_xm/synthesis/xm/synplicity/
sdram_controller_xm/synthesis/xm/synplicity/rev_1/
sdram_controller_xm/synthesis/xm/synplicity/rev_1/sdr_top.edn
sdram_controller_xm/synthesis/xm/synplicity/rev_1/sdr_top.prf
sdram_controller_xm/synthesis/xm/synplicity/rev_1/sdr_top.tlg
sdram_controller_xm/synthesis/xm/synplicity/sdr_top.prd
sdram_controller_xm/synthesis/xm/synplicity/sdr_top.prj
sdram_controller_xm/synthesis/xm/synplicity/sdr_top.tcl
sdram_controller_xm/testbench/
sdram_controller_xm/testbench/readme.txt
sdram_controller_xm/testbench/sdr_tb.tf

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