MIPS instruction set compatible CPU design and simulation

computer_design\design\110\123.cr.mti
...............\......\...\123.mpf
...............\......\...\memfile.dat
...............\......\...\mips.v
...............\......\...\mips.v.bak
...............\......\...\regfile.dat
...............\......\...\transcript
...............\......\...\vsim.wlf
...............\......\...\work\alu\verilog.asm
...............\......\...\....\...\_primary.dat
...............\......\...\....\...\_primary.vhd
...............\......\...\....\...control\verilog.asm
...............\......\...\....\..........\_primary.dat
...............\......\...\....\..........\_primary.vhd
...............\......\...\....\controller\verilog.asm
...............\......\...\....\..........\_primary.dat
...............\......\...\....\..........\_primary.vhd
...............\......\...\....\datapath\verilog.asm
...............\......\...\....\........\_primary.dat
...............\......\...\....\........\_primary.vhd
...............\......\...\....\exmemory\verilog.asm
...............\......\...\....\........\_primary.dat
...............\......\...\....\........\_primary.vhd
...............\......\...\....\flop\verilog.asm
...............\......\...\....\....\_primary.dat
...............\......\...\....\....\_primary.vhd
...............\......\...\....\....en\verilog.asm
...............\......\...\....\......\_primary.dat
...............\......\...\....\......\_primary.vhd
...............\......\...\....\......r\verilog.asm
...............\......\...\....\.......\_primary.dat
...............\......\...\....\.......\_primary.vhd
...............\......\...\....\mips\verilog.asm
...............\......\...\....\....\_primary.dat
...............\......\...\....\....\_primary.vhd
...............\......\...\....\.ux2\verilog.asm
...............\......\...\....\....\_primary.dat
...............\......\...\....\....\_primary.vhd
...............\......\...\....\...4\verilog.asm
...............\......\...\....\....\_primary.dat
...............\......\...\....\....\_primary.vhd
...............\......\...\....\regfile\verilog.asm
...............\......\...\....\.......\_primary.dat
...............\......\...\....\.......\_primary.vhd
...............\......\...\....\top\verilog.asm
...............\......\...\....\...\_primary.dat
...............\......\...\....\...\_primary.vhd
...............\......\...\....\zerodetect\verilog.asm
...............\......\...\....\..........\_primary.dat
...............\......\...\....\..........\_primary.vhd
...............\......\...\....\_info
...............\......\mips.v
...............\......beq\110\123.cr.mti
...............\.........\...\123.mpf
...............\.........\...\memfile.dat
...............\.........\...\mips.v
...............\.........\...\mips.v.bak
...............\.........\...\regfile.dat
...............\.........\...\transcript
...............\.........\...\vsim.wlf
...............\.........\...\work\alu\verilog.asm
...............\.........\...\....\...\_primary.dat
...............\.........\...\....\...\_primary.vhd
...............\.........\...\....\...control\verilog.asm
...............\.........\...\....\..........\_primary.dat
...............\.........\...\....\..........\_primary.vhd
...............\.........\...\....\controller\verilog.asm
...............\.........\...\....\..........\_primary.dat
...............\.........\...\....\..........\_primary.vhd
...............\.........\...\....\datapath\verilog.asm
...............\.........\...\....\........\_primary.dat
...............\.........\...\....\........\_primary.vhd
...............\.........\...\....\exmemory\verilog.asm
...............\.........\...\....\........\_primary.dat
...............\.........\...\....\........\_primary.vhd
...............\.........\...\....\flop\verilog.asm
...............\.........\...\....\....\_primary.dat
...............\.........\...\....\....\_primary.vhd
...............\.........\...\....\....en\verilog.asm
...............\.........\...\....\......\_primary.dat
...............\.........\...\....\......\_primary.vhd
...............\.........\...\....\......r\verilog.asm

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