Verilog CPLD FPGA

BCD_ok-BCD编码
..............\BCD1.asm.rpt
..............\BCD1.done
..............\BCD1.fit.rpt
..............\BCD1.fit.smsg
..............\BCD1.fit.summary
..............\BCD1.flow.rpt
..............\BCD1.map.rpt
..............\BCD1.map.summary
..............\BCD1.pin
..............\BCD1.pof
..............\BCD1.qpf
..............\BCD1.qsf
..............\BCD1.qws
..............\BCD1.sim.rpt
..............\BCD1.tan.rpt
..............\BCD1.tan.summary
..............\BCD1.v
..............\BCD1.vwf
..............\BCD1_assignment_defaults.qdf
..............\BCD计数器.pdf
..............\db
..............\..\BCD1.asm.qmsg
..............\..\BCD1.asm_labs.ddb
..............\..\BCD1.cbx.xml
..............\..\BCD1.cmp.cdb
..............\..\BCD1.cmp.hdb
..............\..\BCD1.cmp.kpt
..............\..\BCD1.cmp.logdb
..............\..\BCD1.cmp.rdb
..............\..\BCD1.cmp.tdb
..............\..\BCD1.cmp0.ddb
..............\..\BCD1.dbp
..............\..\BCD1.db_info
..............\..\BCD1.eco.cdb
..............\..\BCD1.eds_overflow
..............\..\BCD1.fit.qmsg
..............\..\BCD1.hier_info
..............\..\BCD1.hif
..............\..\BCD1.map.cdb
..............\..\BCD1.map.hdb
..............\..\BCD1.map.logdb
..............\..\BCD1.map.qmsg
..............\..\BCD1.pre_map.cdb
..............\..\BCD1.pre_map.hdb
..............\..\BCD1.psp
..............\..\BCD1.rtlv.hdb
..............\..\BCD1.rtlv_sg.cdb
..............\..\BCD1.rtlv_sg_swap.cdb
..............\..\BCD1.sgdiff.cdb
..............\..\BCD1.sgdiff.hdb
..............\..\BCD1.signalprobe.cdb
..............\..\BCD1.sim.hdb
..............\..\BCD1.sim.qmsg
..............\..\BCD1.sim.rdb
..............\..\BCD1.sim_ori.vwf
..............\..\BCD1.sld_design_entry.sci
..............\..\BCD1.sld_design_entry_dsc.sci
..............\..\BCD1.smp_dump.txt
..............\..\BCD1.syn_hier_info
..............\..\BCD1.tan.qmsg
..............\..\wed.zsf

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