13.2 RISC-CPU design 13.3 RISC-CPU Testbench Design

Chapter-13\risc8\alu.v
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..........\.....\regs.v
..........\.....\risc8.cr.mti
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..........\.....\wave\alu.bmp
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..........\.....\....\cpu_test.bmp
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..........\.....\....\idec.bmp
..........\.....\....\pram.bmp
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..........\.....\.ork\alu\verilog.asm
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..........\.....\....\cpu\verilog.asm
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..........\.....\....\exp\verilog.asm
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..........\.....\....\idec\verilog.asm
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..........\.....\....\regs\verilog.asm
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..........\.....\....\risc8.vcd
..........\.....\....\test\verilog.asm
..........\.....\....\....\_primary.dat
..........\.....\....\....\_primary.vhd
..........\.....\....\_info
..........\.....\....\alu
..........\.....\....\cpu
..........\.....\....\cpu_test
..........\.....\....\dram
..........\.....\....\exp
..........\.....\....\idec
..........\.....\....\pram
..........\.....\....\regs
..........\.....\....\test
..........\.....\chart
..........\.....\wave
..........\.....\work
..........\risc8
Chapter-13

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