jpeg ip core for verilog HDL

fpga实现jpeg Verilog源代码\fpga-jpeg\run_length_coding\bench\bench.v.txt
..........................\.........\.................\jpeg_rle.v
..........................\.........\.................\jpeg_rle1.v
..........................\.........\.................\jpeg_rzs.v
..........................\.........\.................\attic\jpeg_rle2.v
..........................\.........\jpeg\bench_top\jpeg_encoder.v
..........................\.........\....\jpeg_encoder.v
..........................\.........\....\sim\Makefile.txt
..........................\.........\....\...\cds.lib
..........................\.........\....\...\hdl.var
..........................\.........\qnr\div_uu.v
..........................\.........\...\jpeg_qnr.v
..........................\.........\...\attic\div.v
..........................\.........\...\.....\div_us.v
..........................\.........\...\.....\ro_cnt.v
..........................\.........\...\.....\ud_cnt.v
..........................\.........\...\div_su.v
..........................\.........\...\bench\bench_div_top.v
..........................\.........\...\.....\timescale.v
..........................\.........\...\.....\bench_qnr_top.v
..........................\.........\rgb2ycrcb\rgb2ycrcb_testbench.v
..........................\.........\.........\rgb2ycrcb.v
..........................\.........\.........\rgb2ycrcb_webAddress.txt
..........................\.........\.........\transcript
..........................\.........\.........\work\_info
..........................\.........\.........\rgb2ycrcb.mpf
..........................\.........\.........\.........\_info
..........................\.........\.........\modelsim.ini
..........................\.........\.........\tcl_stacktrace.txt
..........................\.........\dct\dct.v
..........................\.........\...\dct_cos_table.v
..........................\.........\...\dct_mac.v
..........................\.........\...\dct_syn.v
..........................\.........\...\dctu.v
..........................\.........\...\dctub.v
..........................\.........\...\fdct.v
..........................\.........\...\zigzag.v
..........................\.........\...\ro_cnt.v
..........................\.........\...\ud_cnt.v
..........................\.........\...\dct_bench\bench_top.v
..........................\.........\...\rtl_sim\Makefile.txt
..........................\.........\...\huffman\huffman_dec.v
..........................\.........\...\.......\huffman_enc.v
..........................\.........\...\.......\huffman_tables.v
..........................\.........\...\.......\bench\bench_top.v
..........................\.........\...\.......\.....\generic_dpram.v
..........................\.........\...\.......\.....\generic_fifo_lfsr.v
..........................\.........\...\.......\.....\lfsr.v
..........................\.........\...\.......\.....\timescale.v
..........................\.........\...\.......\bench
..........................\.........\run_length_coding\bench
..........................\.........\.................\attic
..........................\.........\jpeg\bench_top
..........................\.........\....\sim
..........................\.........\qnr\attic
..........................\.........\...\bench
..........................\.........\rgb2ycrcb\work
..........................\.........\.........\rgb2ycrcb
..........................\.........\dct\dct_bench
..........................\.........\...\rtl_sim
..........................\.........\...\huffman
..........................\.........\run_length_coding
..........................\.........\jpeg
..........................\.........\qnr
..........................\.........\rgb2ycrcb
..........................\.........\dct
..........................\fpga-jpeg
fpga实现jpeg Verilog源代码

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