xilink DPD V6.0 IP Core design example

dpd_v6_0_example_design\dfe_base.prj
.......................\dfe_base.vhd
.......................\dpd_v6_0_demo_msdpdgen1p5.cgp
.......................\dpd_v6_0_demo_msdpdgen1p5.ucf
.......................\dpd_v6_0_demo_msdpdgen1p5.xst
.......................\dpd_v6_0_inst.xco
.......................\iter6_pc_cfr_v3_0.xco
.......................\Makefile
.......................\src
.......................\...\clk_gen
.......................\...\.......\hdl
.......................\...\.......\...\clk_gen_src368mhz.vhd
.......................\...\.......\...\data_path_clk_gen_src200mhz.vhd
.......................\...\.......\...\proc_clk_gen_src200mhz.vhd
.......................\...\device
.......................\...\......\common
.......................\...\......\......\hdl
.......................\...\......\......\...\dfe_capture_control.vhd
.......................\...\......\......\...\dfe_complex_fir.vhd
.......................\...\......\......\...\dfe_complex_fir_x0_h0h1.vhd
.......................\...\......\......\...\dfe_complex_fir_x0x1_h0.vhd
.......................\...\......\......\...\dfe_config_registers.vhd
.......................\...\......\......\...\dfe_dlb.vhd
.......................\...\......\......\...\dfe_dlb_wrapper.vhd
.......................\...\......\......\...\dfe_dpram_piped_rtl.vhd
.......................\...\......\......\...\dfe_fh_gen_adder_12x16bit.vhd
.......................\...\......\......\...\dfe_fh_gen_adder_3x48bit.vhd
.......................\...\......\......\...\dfe_gain_iq_mult.vhd
.......................\...\......\......\...\dfe_generic_equalizer.vhd
.......................\...\......\......\...\dfe_glitch_protection.vhd
.......................\...\......\......\...\dfe_pipeliner.vhd
.......................\...\......\......\...\dfe_polyphase_complex_fir.vhd
.......................\...\......\......\...\dfe_rate_change.vhd
.......................\...\......\......\...\dfe_systolic_fir.vhd
.......................\...\......\......\...\dfe_systolic_fir_preadd_coeffs.vhd
.......................\...\......\......\...\dfe_systolic_fir_preadd_data.vhd
.......................\...\......\......\...\dfe_up2.vhd
.......................\...\......\......\...\dfe_up3_dn2.vhd
.......................\...\......\......\...\dfe_up3_dn2_polyphase.vhd
.......................\...\......\......\...\dfe_up3_dn2_polyphase_2x2.vhd
.......................\...\......\......\...\dfe_up3_dn2_polyphase_test.vhd
.......................\...\......\......\...\dpd_dpram.vhd
.......................\...\......\virtex6
.......................\...\......\.......\generic
.......................\...\......\.......\.......\netlist
.......................\...\......\.......\.......\.......\adc_fifo_buffer_8kx12b.ngc
.......................\...\......\.......\.......\.......\fifo_16.ngc
.......................\...\......\.......\.......\.......\fifo_32bit.ngc
.......................\...\......\.......\.......\.......\fifo_48_192.ngc
.......................\...\......\.......\.......\.......\ml605_demo_dlb_complex_mult.ngc
.......................\...\......\.......\.......\.......\srx_fifo_dmux.ngc
.......................\...\......\.......\.......\.......\up2_245_sharp.ngc
.......................\...\......\.......\.......\.......\up3dn2_79taps_2x.ngc
.......................\...\......\.......\.......\.......\up3dn2_79taps_parallel_2.ngc
.......................\...\......\.......\.......\.......\up3dn2_79taps_parallel_3.ngc
.......................\...\......\.......\jtag
.......................\...\......\.......\....\netlist
.......................\...\......\.......\....\.......\jtagcosim_shmem.ngc
.......................\...\......\.......\pc_cfr
.......................\...\......\.......\......\hdl
.......................\...\......\.......\......\...\dfe_cfr_wrapper.vhd
.......................\...\dpd_v6_0
.......................\...\........\debug_if
.......................\...\........\........\create_wrapper.pl
.......................\...\........\........\debug_interface.vhd
.......................\...

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