Northern Computer Composition of seven experiments project6 file

p6
..\Project6 VerilogHDL开发多周期处理器(V1.0@2013.12.08).pdf
..\code.txt
..\control
..\.......\ctrl.v
..\.......\ctrl.v.bak
..\datapath
..\........\alu.v
..\........\alu.v.bak
..\........\be.v
..\........\be.v.bak
..\........\code.txt
..\........\dm.v
..\........\dm.v.bak
..\........\ext.v
..\........\ext.v.bak
..\........\gpr.v
..\........\gpr.v.bak
..\........\im.v
..\........\im.v.bak
..\........\mux.v
..\........\mux.v.bak
..\........\npc.v
..\........\npc.v.bak
..\........\pc.v
..\........\pc.v.bak
..\........\shift.v
..\........\shift.v.bak
..\head
..\....\head_mips.v
..\....\head_mips.v.bak
..\mips.v
..\textbench_mips.v

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