DE2_115_WEB_SERVER_RGMII_ENET0:Gigabit Ethernet, ALTERA DE2 board network communications company, to achieve control of the PC board level digital tube LED/LCD screen display (RGMII)

DE2_115_WEB_SERVER_RGMII_ENET0\.qsys_edit\filters.xml
..............................\..........\preferences.xml
..............................\ddr_o.bsf
..............................\ddr_o.qip
..............................\ddr_o.v
..............................\ddr_o_bb.v
..............................\de2_115_golden_sopc.sdc
..............................\de2_115_golden_sopc.v
..............................\........WEB_Qsys\synthesis\de2_115_WEB_Qsys.qip
..............................\................\.........\de2_115_WEB_Qsys.v
..............................\................\.........\submodules\altera_avalon_dc_fifo.v
..............................\................\.........\..........\altera_avalon_mm_clock_crossing_bridge.v
..............................\................\.........\..........\altera_avalon_sc_fifo.v
..............................\................\.........\..........\altera_avalon_st_clock_crosser.v
..............................\................\.........\..........\altera_avalon_st_handshake_clock_crosser.v
..............................\................\.........\..........\altera_avalon_st_pipeline_base.v
..............................\................\.........\..........\altera_dcfifo_synchronizer_bundle.v
..............................\................\.........\..........\altera_irq_clock_crosser.sv
..............................\................\.........\..........\altera_merlin_arbitrator.sv
..............................\................\.........\..........\altera_merlin_burst_adapter.sv
..............................\................\.........\..........\altera_merlin_burst_uncompressor.sv
..............................\................\.........\..........\altera_merlin_master_agent.sv
..............................\................\.........\..........\altera_merlin_master_translator.sv
..............................\................\.........\..........\altera_merlin_slave_agent.sv
..............................\................\.........\..........\altera_merlin_slave_translator.sv
..............................\................\.........\..........\altera_merlin_std_arbitrator_core.sv
..............................\................\.........\..........\altera_merlin_traffic_limiter.sv
..............................\................\.........\..........\altera_merlin_width_adapter.sv
..............................\................\.........\..........\altera_reset_controller.sdc
..............................\................\.........\..........\altera_reset_controller.v
..............................\................\.........\..........\altera_reset_synchronizer.v
..............................\................\.........\..........\altera_tristate_controller_aggregator.sv
..............................\................\.........\..........\altera_tristate_controller_translator.sv
..............................\................\.........\..........\altera_tse_align_sync.v
..............................\................\.........\..........\altera_tse_alt2gxb_arriagx.v
..............................\................\.........\..........\altera_tse_alt2gxb_basic.v
..............................\................\.........\..........\altera_tse_alt2gxb_gige.v
..............................\................\.........\..........\altera_tse_alt2gxb_gige_wo_rmfifo.v
..............................\................\.........\..........\altera_tse_alt4gxb_gige.v
..............................\................\.........\..........\altera_tse_alt4gxb_gige_wo_rmfifo.v
..............................\................\.........\..........\altera_tse_altgx_civgx_gige.v
..............................\................\.........\..........\altera_tse_altgx_civgx_gige_wo_rmfifo.v
..............................\................\.........\..........\altera_tse_altshifttaps.v
..............................\................\.........\..........\altera_tse_altsyncram_dpm_fifo.v
..............................\................\.........\..........\altera_tse_avst_to_gmii_if.v
..........................

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