this code is verilog digtial system progre

Verilog数字系统设计教程夏宇闻例题源文件\例题源文件\下册例题\关于下册例题的说明.doc
.......................................\..........\........\练习1-9.doc
.......................................\..........\........\练习10.doc
.......................................\..........\........\练习11.doc
.......................................\..........\........\练习12.doc
.......................................\..........\上册例题\关于上册例题的说明.doc
.......................................\..........\........\第10章例题.doc
.......................................\..........\........\第11章例题.doc
.......................................\..........\........\第12章例题.doc
.......................................\..........\........\第13章例题.doc
.......................................\..........\........\第14章例题.doc
.......................................\..........\........\第15章例题.doc
.......................................\..........\........\第16章例题.doc
.......................................\..........\........\第18章例题.doc
.......................................\..........\........\第2章例题.doc
.......................................\..........\........\第4章例题.doc
.......................................\..........\........\第5章例题.doc
.......................................\..........\........\第6章例题.doc
.......................................\..........\........\第7章例题.doc
.......................................\..........\........\第8章例题.doc
.......................................\..........\........\第9章例题.doc
.......................................\..........\........\..17章例题\RiscCpu\accum.v
.......................................\..........\........\..........\.......\addr_decode.v
.......................................\..........\........\..........\.......\adr.v
.......................................\..........\........\..........\.......\alu.v
.......................................\..........\........\..........\.......\clk_gen.v
.......................................\..........\........\..........\.......\counter.v
.......................................\..........\........\..........\.......\cpu.v
.......................................\..........\........\..........\.......\cputop.v
.......................................\..........\........\..........\.......\datactl.v
.......................................\..........\........\..........\.......\machine.v
.......................................\..........\........\..........\.......\machinectl.v
.......................................\..........\........\..........\.......\ram.v
.......................................\..........\........\..........\.......\register.v
.......................................\..........\........\..........\.......\rom.v
.......................................\..........\........\..........\.......\test1.dat
.......................................\..........\........\..........\.......\test1.pro
.......................................\..........\........\..........\.......\test2.dat
.......................................\..........\........\..........\.......\test2.pro
.......................................\..........\........\..........\.......\test3.dat
.......................................\..........\........\..........\.......\test3.pro
.......................................\..........\........\...6章例题\I2Cdesign\addr.dat
.......................................\..........\........\..........\.........\data.dat
.......................................\..........\........\..........\.........\eeprom.v
.......................................\..........\........\..........\.........\eeprom_wr.v
.......................................\..........\........\..........\.........\signal.v
.......................................\..........\........\..........\.........\top.v
.......................................\..........\........\...7章例题\RiscCpu
.......................................\..........\........\...6章例题\I2Cdesign
.......................................\..........\.......

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