Verilog prepared with 8 simple CPU code, to achieve a simple addition and subtraction, memory operations, as well as register operations.

cpu5.10_modelsim\accum.v
................\addr_decode.v
................\adr.v
................\alu.v
................\clk_gen.v
................\clk_gen.v.bak
................\counter.v
................\cpu.asm.rpt
................\cpu.done
................\cpu.eda.rpt
................\cpu.fit.rpt
................\cpu.fit.smsg
................\cpu.fit.summary
................\cpu.flow.rpt
................\cpu.map.rpt
................\cpu.map.smsg
................\cpu.map.summary
................\cpu.pin
................\cpu.qpf
................\cpu.qsf
................\cpu.qws
................\cpu.sof
................\cpu.sta.rpt
................\cpu.sta.summary
................\cpu.v
................\cpu.v.bak
................\cpu.vo
................\cputop.v
................\cputop.v.bak
................\cpu_nativelink_simulation.rpt
................\datactl.v
................\.b\cpu.asm.qmsg
................\..\cpu.asm_labs.ddb
................\..\cpu.cbx.xml
................\..\cpu.cmp.bpm
................\..\cpu.cmp.cdb
................\..\cpu.cmp.ecobp
................\..\cpu.cmp.hdb
................\..\cpu.cmp.kpt
................\..\cpu.cmp.logdb
................\..\cpu.cmp.rdb
................\..\cpu.cmp_merge.kpt
................\..\cpu.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
................\..\cpu.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
................\..\cpu.db_info
................\..\cpu.eco.cdb
................\..\cpu.eda.qmsg
................\..\cpu.fit.qmsg
................\..\cpu.hier_info
................\..\cpu.hif
................\..\cpu.lpc.html
................\..\cpu.lpc.rdb
................\..\cpu.lpc.txt
................\..\cpu.map.bpm
................\..\cpu.map.cdb
................\..\cpu.map.ecobp
................\..\cpu.map.hdb
................\..\cpu.map.kpt
................\..\cpu.map.logdb
................\..\cpu.map.qmsg
................\..\cpu.map_bb.cdb
................\..\cpu.map_bb.hdb
................\..\cpu.map_bb.logdb
................\..\cpu.pre_map.cdb
................\..\cpu.pre_map.hdb
................\..\cpu.rpp.qmsg
................\..\cpu.rtlv.hdb
................\..\cpu.rtlv_sg.cdb
................\..\cpu.rtlv_sg_swap.cdb
................\..\cpu.sgate.rvd
................\..\cpu.sgate_sm.rvd
................\..\cpu.sgdiff.cdb
................\..\cpu.sgdiff.hdb
................\..\cpu.sld_design_entry.sci
................\..\cpu.sld_design_entry_dsc.sci
................\..\cpu.smp_dump.txt
................\..\cpu.sta.qmsg
................\..\cpu.sta.rdb
................\..\cpu.sta_cmp.8_slow_1200mv_85c.tdb
................\..\cpu.syn_hier_info
................\..\cpu.tiscmp.fastest_slow_1200mv_0c.ddb
................\..\cpu.tiscmp.fastest_slow_1200mv_85c.ddb
................\..\cpu.tiscmp.fast_1200mv_0c.ddb
................\..\cpu.tiscmp.slow_1200mv_0c.ddb
................\..\cpu.tiscmp.slow_1200mv_85c.ddb
................\..\cpu.tis_db_list.ddb
................\..\cpu.tmw_info
................\..\cpu_global_asgn_op.abo
................\..\prev_cmp_cpu.asm.qmsg
................\..\prev_cmp_cpu.eda.qmsg
................\..\prev_cmp_cpu.fit.qmsg
................\..\prev_cmp_cpu.map.qmsg
................\..\prev_cmp_cpu.qmsg
................\..\prev_cmp_cpu.sta.qmsg
................\incremental_db\compiled_partitions\cpu.root_partition.cmp.atm
................\..............\...................\cpu.root_partition.cmp.dfp
................\..............\...................\cpu.root_partition.cmp.hdbx
................\..............\...................\cpu.root_partition.cmp.kpt
................\..............\...................\cpu.root_partition.cmp.logdb
................\..............\...................\cpu.root_partition.cmp.rcf

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