My package named design DDR2 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor

ddr_data_path.v
ddr_sdram.v
ddr_sdram_tb.v
Params.v
pll1.v
altclklock.v
ddr_Command.v
ddr_control_interface.v

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