All the supporting source code routines crazy bingo Han Bin will be published book FPGA design techniques and case development explain in the video, mainly relates to the development direction of.

Crazy_FPGA_Examples\01_Counter_Design\dev\Counter_Design.qpf
...................\.................\...\Counter_Design.qsf
...................\.................\...\Counter_Design.qws
...................\.................\...\output_files\Counter_Design.asm.rpt
...................\.................\...\............\Counter_Design.done
...................\.................\...\............\Counter_Design.fit.rpt
...................\.................\...\............\Counter_Design.fit.smsg
...................\.................\...\............\Counter_Design.fit.summary
...................\.................\...\............\Counter_Design.flow.rpt
...................\.................\...\............\Counter_Design.jdi
...................\.................\...\............\Counter_Design.map.rpt
...................\.................\...\............\Counter_Design.map.summary
...................\.................\...\............\Counter_Design.pin
...................\.................\...\............\Counter_Design.sof
...................\.................\...\............\Counter_Design.sta.rpt
...................\.................\...\............\Counter_Design.sta.summary
...................\.................\...\VIP_System.sdc
...................\.................\...\VIP_System.sdc.bak
...................\.................\sim\Counter_Design_TB\Counter_Design.v
...................\.................\...\.................\Counter_Design_TB.cr.mti
...................\.................\...\.................\Counter_Design_TB.mpf
...................\.................\...\.................\Counter_Design_TB.v
...................\.................\...\.................\transcript
...................\.................\...\.................\vsim.wlf
...................\.................\...\.................\vsim_stacktrace.vstf
...................\.................\...\.................\wave.do
...................\.................\...\.................\.ork\@counter_@design\verilog.prw
...................\.................\...\.................\....\................\verilog.psm
...................\.................\...\.................\....\................\_primary.dat
...................\.................\...\.................\....\................\_primary.dbs
...................\.................\...\.................\....\................\_primary.vhd
...................\.................\...\.................\....\................_@t@b\verilog.prw
...................\.................\...\.................\....\.....................\verilog.psm
...................\.................\...\.................\....\.....................\_primary.dat
...................\.................\...\.................\....\.....................\_primary.dbs
...................\.................\...\.................\....\.....................\_primary.vhd
...................\.................\...\.................\....\_info
...................\.................\...\.................\....\.temp\vlog19ssna
...................\.................\...\.................\....\.....\vlog2zrsty
...................\.................\...\.................\....\.....\vlogik2gwb
...................\.................\...\.................\....\_vmake
...................\.................\.rc\Counter_Design.v
...................\.................\...\Counter_Design.v.bak
...................\.2-1_LED_Display_Design_8BitAddr\dev\LED_Display_Design.qpf
...................\................................\...\LED_Display_Design.qsf
...................\................................\...\LED_Display_Design.qws
...................\................................\...\LED_Display_Design.tcl
...................\................................\...\output_files\LED_Display_Design.asm.rpt
...................\................................\...\............\LED_Display_Design.cdf
...................\................................\...\............\LED_Display_Design.done
...................\................................\...\............\LED_Displ

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