The digital wideband receiver is a critical component in modern digital receivers. The receiver has the capability to expose and distinguish adverse signals contained within a large bandwidth (on the order of 1 GHz or more) of the radio frequency (RF) spectrum. The spectral estimator is a highly important design element imperative to the detection of the hostile signals within the intended bandwidth in order to fulfill mission requirements. This crucial element of an FFT-based digital receiver presented several challenges in the development of this research. The task at hand was to minimize the total hardware consumption contributed to the complex arithmetic operations while maintaining a high single signal spurious-free dynamic range (SFDR) and multi-tone instantaneous dynamic range (IDR).

FPGA DESIGN OF A HARDWARE EFFICIENT PIPELINED FFT PROCESSOR3.pdf

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