AES encryption algorithm realize Verilog module password security system as an important part of its core mission is to encrypt the data. AES block cipher algorithm for its high efficiency, low overhead, simple features such as the current password is widely used in research and development modules. Password modules are generally designed to host external serial or parallel port of a hardware device or a card with a high speed, low latency characteristics. From the overall development trend, the embedded code module as a result of flexible and applicable to many user terminals, communications equipment and weapons platforms, will be more widely applied

Packet : 7941945aes_core.rar filelist
aes_core\bench\CVS\Entries
aes_core\bench\CVS\Repository
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aes_core\bench\verilog\test_bench_top.v
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aes_core\doc\aes.pdf
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aes_core\rtl\verilog\aes_cipher_top.v
aes_core\rtl\verilog\aes_inv_cipher_top.v
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aes_core

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