OFDM system with a FPGA implementation, hardware language Verilog, environment xilinx, details of receiver and transmitter modules source code

基于Xilinx FPGA的OFDM通信系统基带设计\Receiver\CFO_Correction.rar
.....................................\........\Channel_Equalizer.rar
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.....................................\........\Viterbi.rar
.....................................\Transmitter\clock_generator\clock_generator\clk_generator_summary.html
.....................................\...........\...............\...............\clock_generator.ise
.....................................\...........\...............\...............\clock_generator.ise_ISE_Backup
.....................................\...........\...............\...............\clock_generator.restore
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.....................................\...........\CP_ADDER\bram1I.asy
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.....................................\...........\........\bram2r.asy
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.....................................\...........\........\bram2r.v
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.....................................\...........\........\bram2r.vhd
.....................................\...........\........\bram2r.vho
.....................................\...........\........\bram2r.xco
.....................................\...........\........\CP_ADDER.ise
.....................................\...........\........\CP_ADDER.ise_ISE_Backup
.....................................\...........\........\CP_ADDER.restore
.....................................\...........\........\CP_adder.v
.....................................\...........\........\CP_adder_summary.html
.....................................\...........\........\templa

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