timing design

Ex1_Multicycle
..............\clock_enable_multicycle.bdf
..............\clock_enable_multicycle.qpf
..............\clock_enable_multicycle.qsf
..............\clock_enable_multicycle.sdc
..............\Solutions
..............\.........\clock_enable_multicycle_solution.sdc
Ex2_SSI_SDR
...........\Scripts
...........\.......\input_analysis.tcl
...........\.......\output_analysis.tcl
...........\sfi_41.pin
...........\sfi_41.qpf
...........\sfi_41.qsf
...........\sfi_41.sdc
...........\sfi_41.sdc.bak
...........\sfi_41.v
...........\sfi_pll.ppf
...........\sfi_pll.qip
...........\sfi_pll.v
...........\Solutions
...........\.........\sfi_41_solution.sdc
...........\.........\sfi_41_solution.sdc.bak
...........\tx_ddio_1.ppf
...........\tx_ddio_1.qip
...........\tx_ddio_1.v
...........\tx_ddio_16.ppf
...........\tx_ddio_16.qip
...........\tx_ddio_16.v
Ex3_SSI_DDR
...........\rgmii.qpf
...........\rgmii.qsf
...........\rgmii.sdc
...........\rgmii.v
...........\rgmii_assignment_defaults.qdf
...........\RX_DDIO.ppf
...........\RX_DDIO.v
...........\rx_pll.ppf
...........\rx_pll.qip
...........\rx_pll.v
...........\Solutions
...........\.........\rgmii_solution.sdc
...........\TX_DDIO.ppf
...........\TX_DDIO.v
...........\TX_DDIO_CLK.ppf
...........\TX_DDIO_CLK.qip
...........\TX_DDIO_CLK.v
...........\tx_pll.ppf
...........\tx_pll.qip
...........\tx_pll.v
Ex4_Feedback
............\clock_feedback_assp.bdf
............\clock_feedback_assp.qpf
............\clock_feedback_assp.qsf
............\clock_feedback_assp.sdc
............\clock_feedback_assp_assignment_defaults.qdf
............\pll_fpga_assp.bsf
............\pll_fpga_assp.ppf
............\pll_fpga_assp.qip
............\pll_fpga_assp.v
............\pll_fpga_assp_bb.v
............\pll_fpga_assp_inst.v
............\Solutions
............\.........\clock_feedback_assp_solution.sdc
Ex5_LVDS
........\diff_io_top.qpf
........\diff_io_top.qsf
........\diff_io_top.sdc
........\diff_io_top.v
........\fir.html
........\fir.qip
........\fir.v
........\fir_ast.vhd
........\fir_coef_0.hex
........\fir_coef_0_inv.hex
........\fir_coef_1.hex
........\fir_coef_1_inv.hex
........\fir_compiler-library
........\....................\accum.v
........\....................\addr_cnt_dn.v
........\....................\addr_cnt_dn_poly.v
........\....................\addr_cnt_up.v
........\....................\at_sink_mod.v
........\....................\at_sink_mod_bin.v
........\....................\at_sink_mod_par.v
........\....................\at_src_mod.v
........\....................\at_src_mod_par.v
........\....................\auk_dspip_avalon_streaming_block_sink_fir_100.vhd
........\....................\auk_dspip_avalon_streaming_block_source_fir_100.vhd
........\....................\auk_dspip_avalon_streaming_controller_fir_100.vhd
........\....................\auk_dspip_avalon_streaming_controller_pe_fir_100.vhd
........\....................\auk_dspip_avalon_streaming_monitor_fir_100.vhd
........\....................\auk_dspip_avalon_streaming_sink_fir_100.ocp
........\....................\auk_dspip_avalon_streaming_sink_fir_100.vhd
........\....................\auk_dspip_avalon_streaming_sink_model_fir_100.vhd
........\....................\auk_dspip_avalon_streaming_source_fir_100.vhd
........\....................\auk_dspip_avalon_streaming_source_from_monitor_fir_100.vhd
........\....................\auk_dspip_avalon_streaming_source_model_fir_100.vhd
........\....................\auk_dspip_delay_fir_100.vhd
........\....................\auk_dspip_fast_accumulator_fir_100.vhd

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