Introduction - If you have any usage issues, please Google them yourself
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY chenyongqiang IS
PORT ( CLK : IN STD_LOGIC
SG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) 段控制信号输出
BT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) 位控制信号输出
END
ARCHITECTURE one OF chenyongqiang IS
SIGNAL CNT8 : STD_LOGIC_VECTOR(2 DOWNTO 0)
SIGNAL A : INTEGER RANGE 0 TO 15
BEGIN
P1: PROCESS( CNT8 )
BEGIN
CASE CNT8 IS
WHEN 000 => BT <= 00000001 A <= 1
WHEN 001 => BT <= 00000010 A <= 2
WHEN 010 => BT <= 00000100 A <= 3
WHEN 011 => BT <= 00001000 A <= 4
WHEN 100 => BT <= 00010000 A <= 5
WHEN 101 => BT <= 00100000 A <= 6
WHEN 110 => BT <= 01000000 A <= 7
WHEN 111 => BT <= 10000000 A <= 8
WHEN OTHERS => NULL
END CASE
END PROCESS P1
P2: PROCESS(CLK)
BEGIN
IF CLK EVENT AND CLK = 1 THEN CNT8 <= CNT8+ 1
END IF
END PROCESS P2
P3: PROCESS( A