The FPGA 10 m/100 m/1000 m Ethernet IP core source code, an external 88 e1111phy chip simulation verification, is very useful for developers FPGA Ethernet MAC layer

ethernet_tri_mode
.................\tags
.................\....\arelease
.................\....\........\doc
.................\....\........\...\RGMII_DataSheet.pdf
.................\....\rel-1-0
.................\....\.......\bench
.................\....\.......\.....\verilog
.................\....\.......\.....\.......\Phy_sim.v
.................\....\.......\.....\.......\User_int_sim.v
.................\....\.......\.....\.......\altera_mf.v
.................\....\.......\.....\.......\host_sim.v
.................\....\.......\.....\.......\reg_int_sim.v
.................\....\.......\.....\.......\tb_top.v
.................\....\.......\doc
.................\....\.......\...\Tri-mode_Ethernet_MAC_Specifications.pdf
.................\....\.......\...\Tri-mode_Ethernet_MAC_Verification_plan.pdf
.................\....\.......\rtl
.................\....\.......\...\verilog
.................\....\.......\...\.......\Clk_ctrl.v
.................\....\.......\...\.......\MAC_rx
.................\....\.......\...\.......\......\Broadcast_filter.v
.................\....\.......\...\.......\......\CRC_chk.v
.................\....\.......\...\.......\......\MAC_rx_FF.v
.................\....\.......\...\.......\......\MAC_rx_add_chk.v
.................\....\.......\...\.......\......\MAC_rx_ctrl.v
.................\....\.......\...\.......\MAC_rx.v
.................\....\.......\...\.......\MAC_top.v
.................\....\.......\...\.......\MAC_tx
.................\....\.......\...\.......\......\CRC_gen.v
.................\....\.......\...\.......\......\MAC_tx_Ctrl.v
.................\....\.......\...\.......\......\MAC_tx_FF.v
.................\....\.......\...\.......\......\MAC_tx_addr_add.v
.................\....\.......\...\.......\......\Ramdon_gen.v
.................\....\.......\...\.......\......\flow_ctrl.v
.................\....\.......\...\.......\MAC_tx.v
.................\....\.......\...\.......\Phy_int.v
.................\....\.......\...\.......\RMON
.................\....\.......\...\.......\....\RMON_addr_gen.v
.................\....\.......\...\.......\....\RMON_ctrl.v
.................\....\.......\...\.......\....\RMON_dpram.v
.................\....\.......\...\.......\RMON.v
.................\....\.......\...\.......\TECH
.................\....\.......\...\.......\....\CLK_DIV2.v
.................\....\.......\...\.......\....\CLK_SWITCH.v
.................\....\.......\...\.......\....\duram.v
.................\....\.......\...\.......\eth_miim.v
.................\....\.......\...\.......\header.v
.................\....\.......\...\.......\miim
.................\....\.......\...\.......\....\eth_clockgen.v
.................\....\.......\...\.......\....\eth_outputcontrol.v
.................\....\.......\...\.......\....\eth_shiftreg.v
.................\....\.......\...\.......\....\timescale.v
.................\....\.......\...\.......\reg_int.v
.................\....\.......\sim
.................\....\.......\...\rtl_sim
.................\....\.......\...\.......\ncsim_sim
.................\....\.......\...\.......\.........\bin
.................\....\.......\...\.......\.........\...\cds.lib
.................\....\.......\...\.......\.........\...\com.nc
.................\....\.......\...\.......\.........\...\config.ini
.................\....\.......\...\.......\.........\...\hdl.var
.................\....\.......\...\.......\.........\...\ip_32W_check.dll
.................\....\.......\...\.......\.........\...\ip_32W_check_vpi.dll
.................\....\.......\...\.......\.........\...\ip_32W_gen.dll
.................\....\.......\...\.......\.........\...\ip_32W_gen_vpi.dll
.................\....\.......\...\.......\.........\...\sim.nc
.................\....\.......\...\.......\.........\...\sim_only.nc
.................\....\.......\...\.......\.........\...\vlog.list
.................\....\.......\...\.......\.........\data
.................\....\.......\...\.......\.........\....\1000Mbps_duplex.vec
.................\....\.......\...\.......\.........\....\100Mbps_duplex.vec
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