Introduction - If you have any usage issues, please Google them yourself
In this system, we discuss the architecture, design, and testing of the
first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid
single flux quantum adder implemented using the ISTEC 10 kA/cm
2ADP2.1 fabrication process. Compared to the Kogge–Stone adder, our
parallel-prefix sparse-tree adder has better energy efficiency with
significantly reduced complexity (at the expense of latency) and almost no
decrease in operation frequency. The 16-bit adder core (without SFQ-to-dc
and dc-to-SFQ converters) has 9941 Josephson junctions occupying an area
of 8.5 mm 2. It is designed for the target operation frequency of 30 GHz
with the expected latency of 352 ps at the bias voltage of 2.5 mV. The adder
chip was fabricated and successfully tested at low frequency for all test
patterns with measured bias margins of +9.8 /− 10.7 .