Basic sequential circuits related procedure, using VHDL

jibenshixu\counta.vhd
..........\counta.vwf
..........\db\add_sub_klh.tdf
..........\..\jibenshixu.asm.qmsg
..........\..\jibenshixu.cbx.xml
..........\..\jibenshixu.cmp.cdb
..........\..\jibenshixu.cmp.hdb
..........\..\jibenshixu.cmp.logdb
..........\..\jibenshixu.cmp.rdb
..........\..\jibenshixu.cmp.tdb
..........\..\jibenshixu.cmp0.ddb
..........\..\jibenshixu.dbp
..........\..\jibenshixu.db_info
..........\..\jibenshixu.eco.cdb
..........\..\jibenshixu.eds_overflow
..........\..\jibenshixu.fit.qmsg
..........\..\jibenshixu.fnsim.cdb
..........\..\jibenshixu.fnsim.hdb
..........\..\jibenshixu.fnsim.qmsg
..........\..\jibenshixu.hier_info
..........\..\jibenshixu.hif
..........\..\jibenshixu.map.cdb
..........\..\jibenshixu.map.hdb
..........\..\jibenshixu.map.logdb
..........\..\jibenshixu.map.qmsg
..........\..\jibenshixu.pre_map.cdb
..........\..\jibenshixu.pre_map.hdb
..........\..\jibenshixu.psp
..........\..\jibenshixu.rtlv.hdb
..........\..\jibenshixu.rtlv_sg.cdb
..........\..\jibenshixu.rtlv_sg_swap.cdb
..........\..\jibenshixu.sgdiff.cdb
..........\..\jibenshixu.sgdiff.hdb
..........\..\jibenshixu.sim.hdb
..........\..\jibenshixu.sim.qmsg
..........\..\jibenshixu.sim.rdb
..........\..\jibenshixu.sim.vwf
..........\..\jibenshixu.sld_design_entry.sci
..........\..\jibenshixu.sld_design_entry_dsc.sci
..........\..\jibenshixu.syn_hier_info
..........\..\jibenshixu.tan.qmsg
..........\..\wed.zsf
..........\dff1.vhd
..........\dff1.vwf
..........\jibenshixu.asm.rpt
..........\jibenshixu.done
..........\jibenshixu.fit.rpt
..........\jibenshixu.fit.summary
..........\jibenshixu.flow.rpt
..........\jibenshixu.map.rpt
..........\jibenshixu.map.summary
..........\jibenshixu.pin
..........\jibenshixu.pof
..........\jibenshixu.qpf
..........\jibenshixu.qsf
..........\jibenshixu.qws
..........\jibenshixu.sim.rpt
..........\jibenshixu.sof
..........\jibenshixu.tan.rpt
..........\jibenshixu.tan.summary
..........\db
jibenshixu

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