VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later

Packet : 1191286598b_10b.rar filelist
8b_10b\8b10b_encdec_v1d0[1].pdf
8b_10b\8b10_dec.vhd
8b_10b\8b10_enc.vhd
8b_10b\encdec_8b10b_TB.vhd
8b_10b\enc_8b10b_TB.vhd
8b_10b

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