des code source vhdl sur fpga

design_files\starterkit
............\..........\DE1-SoC
............\..........\.......\Altera_UP_Audio_Bit_Counter.v
............\..........\.......\Altera_UP_Audio_In_Deserializer.v
............\..........\.......\Altera_UP_Audio_Out_Serializer.v
............\..........\.......\Altera_UP_Clock_Edge.v
............\..........\.......\Altera_UP_I2C.v
............\..........\.......\Altera_UP_I2C_AV_Auto_Initialize.v
............\..........\.......\Altera_UP_I2C_DC_Auto_Initialize.v
............\..........\.......\Altera_UP_I2C_LCM_Auto_Initialize.v
............\..........\.......\Altera_UP_Slow_Clock_Generator.v
............\..........\.......\Altera_UP_SYNC_FIFO.v
............\..........\.......\audio_and_video_config.v
............\..........\.......\audio_codec.v
............\..........\.......\clock_generator.v
............\..........\.......\part1.qpf
............\..........\.......\part1.qsf
............\..........\.......\part1.vhd
............\..........\DE2-115
............\..........\.......\Altera_UP_Audio_Bit_Counter.v
............\..........\.......\Altera_UP_Audio_In_Deserializer.v
............\..........\.......\Altera_UP_Audio_Out_Serializer.v
............\..........\.......\Altera_UP_Clock_Edge.v
............\..........\.......\Altera_UP_I2C.v
............\..........\.......\Altera_UP_I2C_AV_Auto_Initialize.v
............\..........\.......\Altera_UP_I2C_DC_Auto_Initialize.v
............\..........\.......\Altera_UP_I2C_LCM_Auto_Initialize.v
............\..........\.......\Altera_UP_Slow_Clock_Generator.v
............\..........\.......\Altera_UP_SYNC_FIFO.v
............\..........\.......\audio_and_video_config.v
............\..........\.......\audio_codec.v
............\..........\.......\clock_generator.v
............\..........\.......\part1.qpf
............\..........\.......\part1.qsf
............\..........\.......\part1.vhd

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