With the reduced width of the process, timing issues began to dominate the IC design. In order to solve the interconnect delay full-chip, full-chip analysis and optimization needs: Pr im eT im e S yn oP sys is a wholly-chip and gate-level static timing analysis tools. Pr im eTi me to analyze large synchronous digital ASIC. Static timing analysis is a thorough analysis, debug, verification, design methods

ASIC设计中的静态时序分析技术_唐振宇.pdf

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