Packet : 97288423de2_ccd.rar filelist
DE2_CCD\CCD_Capture.v
DE2_CCD\DE2_CCD.asm.rpt
DE2_CCD\DE2_CCD.cdf
DE2_CCD\DE2_CCD.done
DE2_CCD\DE2_CCD.dpf
DE2_CCD\DE2_CCD.fit.eqn
DE2_CCD\DE2_CCD.fit.rpt
DE2_CCD\DE2_CCD.fit.smsg
DE2_CCD\DE2_CCD.fit.summary
DE2_CCD\DE2_CCD.flow.rpt
DE2_CCD\DE2_CCD.map.eqn
DE2_CCD\DE2_CCD.map.rpt
DE2_CCD\DE2_CCD.map.summary
DE2_CCD\DE2_CCD.pin
DE2_CCD\DE2_CCD.pof
DE2_CCD\DE2_CCD.qpf
DE2_CCD\DE2_CCD.qsf
DE2_CCD\DE2_CCD.qws
DE2_CCD\DE2_CCD.sof
DE2_CCD\DE2_CCD.tan.rpt
DE2_CCD\DE2_CCD.tan.summary
DE2_CCD\DE2_CCD.v
DE2_CCD\DE2_CCD_assignment_defaults.qdf
DE2_CCD\I2C_CCD_Config.v
DE2_CCD\I2C_Controller.v
DE2_CCD\Line_Buffer.v
DE2_CCD\Mirror_Col.v
DE2_CCD\RAW2RGB.v
DE2_CCD\Reset_Delay.v
DE2_CCD\SEG7_LUT.v
DE2_CCD\SEG7_LUT_8.v
DE2_CCD\sopc_builder_debug_log.txt
DE2_CCD\Stack_RAM.v
DE2_CCD\VGA_Controller.v
DE2_CCD\VGA_Param.h
DE2_CCD\transcript
DE2_CCD\Sdram_Control_4Port\command.v
DE2_CCD\Sdram_Control_4Port\control_interface.v
DE2_CCD\Sdram_Control_4Port\Sdram_Control_4Port.v
DE2_CCD\Sdram_Control_4Port\Sdram_FIFO.v
DE2_CCD\Sdram_Control_4Port\Sdram_Params.h
DE2_CCD\Sdram_Control_4Port\Sdram_PLL.v
DE2_CCD\Sdram_Control_4Port\sdr_data_path.v
DE2_CCD\Sdram_Control_4Port
DE2_CCD\db\altsyncram_3731.tdf
DE2_CCD\db\altsyncram_4m81.tdf
DE2_CCD\db\altsyncram_9cn1.tdf
DE2_CCD\db\altsyncram_drg1.tdf
DE2_CCD\db\alt_synch_pipe_ud8.tdf
DE2_CCD\db\alt_synch_pipe_vd8.tdf
DE2_CCD\db\a_gray2bin_kdb.tdf
DE2_CCD\db\a_graycounter_i27.tdf
DE2_CCD\db\a_graycounter_j27.tdf
DE2_CCD\db\a_graycounter_o96.tdf
DE2_CCD\db\cntr_3rf.tdf
DE2_CCD\db\dcfifo_5jj1.tdf
DE2_CCD\db\dffpipe_oe9.tdf
DE2_CCD\db\dffpipe_pe9.tdf
DE2_CCD\db\dffpipe_qe9.tdf
DE2_CCD\db\shift_taps_gkn.tdf
DE2_CCD\db\DE2_CCD.db_info
DE2_CCD\db\DE2_CCD.map.qmsg
DE2_CCD\db\DE2_CCD.sld_design_entry.sci
DE2_CCD\db\DE2_CCD.eco.cdb
DE2_CCD\db
DE2_CCD\.sopc_builder\install.ptf
DE2_CCD\.sopc_builder
DE2_CCD\CCD.ptf
DE2_CCD\CCD.v
DE2_CCD\CCD.ptf.6.00
DE2_CCD\CCD.ptf.bak
DE2_CCD\DE2_CCD.bsf
DE2_CCD\30RGB2RGB8.v
DE2_CCD

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