Wireless communication FPGA design, a book of verilog code with matlab code, very useful good information, this book is the direction of digital communication IC must s

《无线通信FPGA设计》书的源代码\matlab代码\matlab\c10\c.mat
..............................\..........\......\...\costas.m
..............................\..........\......\...\frame_syn.m
..............................\..........\......\...\PLLC.m
..............................\..........\......\...\RRCrece.m
..............................\..........\......\...\RRCsend.m
..............................\..........\......\...\symbol_syn.m
..............................\..........\......\..1\adpeq.m
..............................\..........\......\...\ante.m
..............................\..........\......\...\FFTlms.m
..............................\..........\......\...\lms.m
..............................\..........\......\...\RLS.m
..............................\..........\......\...\signlms.m
..............................\..........\......\...\WHT.m
..............................\..........\......\...\WHTlms.m
..............................\..........\......\..2\correce.m
..............................\..........\......\...\matchfil.m
..............................\..........\......\...\rake.m
..............................\..........\......\..3\cell_search_cpich.m
..............................\..........\......\...\ovsf.m
..............................\..........\......\...\scramble.m
..............................\..........\......\...\wcdmasource.m
..............................\..........\......\.6\impinvar_bilinear.m
..............................\..........\......\..\rcosflt_filter.m
..............................\..........\......\..\rcosine_filter.m
..............................\..........\......\.7\cicde.m
..............................\..........\......\..\CICdec.m
..............................\..........\......\..\cicin.m
..............................\..........\......\..\CICinterp.m
..............................\..........\......\..\halfdec.m
..............................\..........\......\..\halfinterp.m
..............................\..........\......\..\hbfil.m
..............................\..........\......\..\multirece.m
..............................\..........\......\..\multisend.m
..............................\..........\......\.8\ASKmod.m
..............................\..........\......\..\F2T.m
..............................\..........\......\..\LPF.m
..............................\..........\......\..\MSKmod.m
..............................\..........\......\..\OFDMmod.m
..............................\..........\......\..\QAMmod.m
..............................\..........\......\..\QPSKmod.m
..............................\..........\......\..\T2F.m
..............................\..........\......\.9\convcode.m
..............................\..........\......\..\CRCcheck.m
..............................\..........\......\..\encoderm.m
..............................\..........\......\..\encode_bit.m
..............................\..........\......\..\hamming7_4.m
..............................\..........\......\..\intrlvcode.m
..............................\..........\......\..\RScode.m
..............................\..........\......\..\rsc_encode.m
..............................\..........\......\..\TCMcode.m
..............................\Verilog代码\c10\10-2\mult.xco
..............................\...........\...\....\mydds.xco
..............................\...........\...\....\square_syn.v
..............................\...........\...\...4\coastas_dds.v
..............................\...........\...\....\costas_lf.v
..............................\...........\...\....\costas_loop.v
..............................\...........\...\....\costas_lpf.v
..............................\...........\...\....\costas_mult.v
..............................\...........\...\....\err_mult.v
..............................\...........\...\....\fir_lpf.xco
..............................\...........\...\....\mult.xco
..............................\...........\...\....\my_dds.xco
..............................\...........\...\...6\dearly_sub.v
..............................\...........\...\....\dedds.v
....

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