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OpenCoreUSB2IP

  • Category : USB develop
  • Tags :
  • Update : 2017-05-02
  • Size : 192kb
  • Downloaded :0次
  • Author :徐****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
OpenCore 的 USB2.0 IP全套资料,包括源代码、设计文档等
Packet file list
(Preview for download)


USB2.0 IP\bench\CVS\Entries
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\verilog\CVS\Entries
.........\.....\.......\...\Repository
.........\.....\.......\...\Root
.........\doc\CVS\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\README.txt
.........\...\STATUS.txt
.........\...\usb_doc.pdf
.........\rtl\CVS\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\verilog\CVS\Entries
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\usbf_crc16.v
.........\...\.......\usbf_crc5.v
.........\...\.......\usbf_defines.v
.........\...\.......\usbf_ep_rf.v
.........\...\.......\usbf_ep_rf_dummy.v
.........\...\.......\usbf_idma.v
.........\...\.......\usbf_mem_arb.v
.........\...\.......\usbf_pa.v
.........\...\.......\usbf_pd.v
.........\...\.......\usbf_pe.v
.........\...\.......\usbf_pl.v
.........\...\.......\usbf_rf.v
.........\...\.......\usbf_top.v
.........\...\.......\usbf_utmi_if.v
.........\...\.......\usbf_utmi_ls.v
.........\...\.......\usbf_wb.v
.........\sim\CVS\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\rtl_sim\bin\CVS\Entries
.........\...\.......\...\...\Repository
.........\...\.......\...\...\Root
.........\...\.......\CVS\Entries
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\run\CVS\Entries
.........\...\.......\...\...\Repository
.........\...\.......\...\...\Root
.........\.yn\bin\comp.dc
.........\...\...\CVS\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\...\...\design_spec.dc
.........\...\...\lib_spec.dc
.........\...\...\read.dc
.........\...\CVS\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\log\CVS\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\...\out\CVS\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\...\run\CVS\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\.im\rtl_sim\bin\CVS
.........\...\.......\run\CVS
.........\bench\verilog\CVS
.........\rtl\verilog\CVS
.........\sim\rtl_sim\bin
.........\...\.......\CVS
.........\...\.......\run
.........\.yn\bin\CVS
.........\...\log\CVS
.........\...\out\CVS
.........\...\run\CVS
.........\bench\CVS
.........\.....\verilog
.........\doc\CVS
.........\rtl\CVS
.........\...\verilog
.........\sim\CVS
.........\...\rtl_sim
.........\.yn\bin
.........\...\CVS
.........\...\log
.........\...\out
.........\...\run
.........\bench
.........\doc
.........\rtl
.........\sim
.........\syn
USB2.0 IP
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