TDLTE simulation

TDLTE_PHY_ALL
.............\addawgndnoise.m
.............\Cdblk_concate1.m
.............\cdblk_para_cal.m
.............\Cdblk_seg1.m
.............\CRC_attach.m
.............\CRC_check.m
.............\crc24a.m
.............\de_cdblk_concate.m
.............\de_CRC.m
.............\de_interleave.m
.............\de_mod_dsp.m
.............\de_rateMatch_turbo.m
.............\de_scramble.m
.............\de_turboCode.m
.............\deCdblk_rateMatch_turbo.m
.............\deCdblk_turboCode.m
.............\Deremap.m
.............\E_cal.m
.............\equal.m
.............\equal2ant.m
.............\F_DeSub_inter_tc.m
.............\fftantdata.m
.............\G_cal.m
.............\genantdata.m
.............\genFredata.m
.............\interleave.m
.............\interleaver.m
.............\internal_leaver_par.m
.............\lschannel.m
.............\LTE_rx_siso_decode.mexw32
.............\LTE_rx_siso_decode.mexw64
.............\modfun.m
.............\pseudo_random_seq_gen.m
.............\pusch_rs_gen.m
.............\RateMatching.m
.............\RateMatchingFun.m
.............\remap.m
.............\rsc_encode.m
.............\scramblefun.m
.............\Source_data_gen.m
.............\Subblock_interleave_index.m
.............\Test.wmv
.............\TestLoopBack.wmv
.............\Turbo_encoder1.m
.............\TurboEncodeFun.m
.............\UL_DSP_link_main.m

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