This a source code for flash memory in verilog and the flash memory used is samsung k9 whose module can be found online

N25Q00AA13E_VG13
................\cds.lib
................\code
................\....\N25Qxxx.v
................\doc
................\hdl.var
................\include
................\.......\.DevParam.h.swp
................\.......\.UserData.h.swp
................\.......\Decoders.h
................\.......\DevParam.h
................\.......\PLRSDetectors.h
................\.......\StackDecoder.h
................\.......\TimingData.h
................\.......\UserData.h
................\Micron_1.cr.mti
................\Micron_1.mpf
................\path.txt
................\readme.txt
................\run_modelsim
................\run_ncsim
................\run_vcs
................\sim
................\...\.restartSimSession.tcl.old
................\...\.simvision
................\...\..........\dbrowser-bookmarks
................\...\..........\schematic-bookmarks
................\...\..........\source-bookmarks
................\...\mem_Q1024.vmf
................\...\mem_Q512.vmf
................\...\session.inter.vpd.tcl
................\...\sfdp.vmf
................\...\wave.do
................\stim
................\....\.SYNC
................\....\.....\Contents
................\....\dummy_prova.v
................\....\erase.v
................\....\lock1.v
................\....\lock2.v
................\....\lock_test_SR.v
................\....\otp.v
................\....\program.v
................\....\read.v
................\....\Readme.txt
................\....\read_dtr.v
................\....\test_address_mode.v
................\....\test_protocol.v
................\....\XIP_Numonyx.v
................\top
................\...\.SYNC
................\...\.....\Contents
................\...\ClockGenerator.v
................\...\StimGen_interface.h
................\...\StimTasks.v
................\...\Testbench.v
................\vsim.wlf
................\vsim_stacktrace.vstf
................\work
................\....\_info
................\....\_lib.qdb
................\....\_lib1_1.qdb
................\....\_lib1_1.qpg
................\....\_lib1_1.qtl
................\....\_vmake

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