Experimental purpose: Familiar with ISE8.2 development environment, master the method of Engineering generation; Familiar with SEED-XDTK_V4 experiment environment; Understanding the HDL implementation of LCD; Understanding the use of the Memory module. Experiment content: Generation and instantiation of memory module of FPGA; System clock design; LCD light up.

需要的文件\CLK_DIV.v
需要的文件\hezhongda.coe
需要的文件\LCD_DISPLAY.v
需要的文件\LCD_WRITE.v
需要的文件\main.ucf
需要的文件\main.v
需要的文件\v4_dcm.v
需要的文件\v4_lcd_ziku.v
需要的文件\v4_lcd_ziku.xco
需要的文件\复件 v4_lcd_ziku.v
需要的文件
27NJU6450A.pdf
FPGA设计与应用实验（硬件综合）.ppt
LCM122326说明.pdf

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