Using Hardware Description Language Verilog prepared by the mosaic process, the Bayer format into RGB format.

bilinear_demosaic\branches
bilinear_demosaic\tags
bilinear_demosaic\trunk
bilinear_demosaic\trunk\doc
bilinear_demosaic\trunk\rtl
bilinear_demosaic\trunk\rtl\verilog
bilinear_demosaic\trunk\rtl\verilog\bilinearDemosaic.v
bilinear_demosaic\trunk\rtl\verilog\registerDelay.v
bilinear_demosaic\trunk\sim
bilinear_demosaic\trunk\sim\rtl_sim
bilinear_demosaic\trunk\sim\rtl_sim\bilinearDemosaic.v
bilinear_demosaic\trunk\sim\rtl_sim\bilinearDemosaic.v.bak
bilinear_demosaic\trunk\sim\rtl_sim\demosaic.cr.mti
bilinear_demosaic\trunk\sim\rtl_sim\demosaic.mpf
bilinear_demosaic\trunk\sim\rtl_sim\demosaic_tb.v
bilinear_demosaic\trunk\sim\rtl_sim\demosaic_tb.v.bak
bilinear_demosaic\trunk\sim\rtl_sim\dst
bilinear_demosaic\trunk\sim\rtl_sim\dst\outputFS.raw
bilinear_demosaic\trunk\sim\rtl_sim\dst\outputIT.raw
bilinear_demosaic\trunk\sim\rtl_sim\dst\outputOT.raw
bilinear_demosaic\trunk\sim\rtl_sim\registerDelay.v
bilinear_demosaic\trunk\sim\rtl_sim\src
bilinear_demosaic\trunk\sim\rtl_sim\src\input640x512RGBBlur.raw
bilinear_demosaic\trunk\sim\rtl_sim\work
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\_deps
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopt0c5b7m
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopt193gwn
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopt1h3mrq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopt4imafq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopt4srdwn
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopt4wt77m
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopt51sirq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopt89e9wn
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopt8bb7cq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopt93feiq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptbb4y7m
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptbv03cq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptcg29sq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptcs36wn
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptcw4bfq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptevsv7m
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptfbn0cq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptg9r5nq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptgct8fq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopti8dxwn
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptigergm
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptjwf5fq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptn21teq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopttbswfq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopttinneq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopttsssvn
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\voptx2cjeq
bilinear_demosaic\trunk\sim\rtl_sim\work\@_opt\vopty0errq
bilinear_demosaic\trunk\sim\rtl_sim\work\_info
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlog3r14v4
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlog4e8wj7
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlog562vr0
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlog56dyts
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlog5mq16n
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlog66sc2b
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlog69abq6
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlog6mhd46
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlog7n5678
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlog7va632
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlog9d769x
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogamj161
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogcn3gkd
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogg52zci
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogjk5f18
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogq7jk9b
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogw79ysx
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogwtsy8r
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogxt020s
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogy843sx
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogz11rh8
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogzvz7qc
bilinear_demosaic\trunk\sim\rtl_sim\work\_temp\vlogzykric
bilinear_demosaic\trunk\sim\rtl_sim\work\_vmake
bilinear_demosaic\trunk\sim\rtl_sim\work\bilinear@demosaic
bilinear_demosaic\trunk\sim\rtl_sim\work\bilinear@demosaic\_primary.dat
bilinear_demosaic\trunk\sim\rtl_sim\work\bilinear@demosaic\_primary.dbs
bilinear_demosaic\trunk\sim\rtl_sim\work\bilinear@demosaic\_primary.vhd
bilinear_demosaic\trunk\sim\rtl_sim\work\bilinear@demosaic\verilog.asm
bilinear_demosaic\trunk\sim\rtl_sim\work\bilinear@demosaic\verilog.rw
bilinear_demosaic\trunk\sim\rtl_sim\work\demosaic@test
bilinear_demosaic\trunk\sim\rtl_sim\work\demosaic@test\_primary.dat
bilinear_demosaic\trunk\sim\rtl_sim\work\demosaic@test\_primary.dbs
bilinear_demosaic\trunk\sim\rtl_sim\work\demosaic@test\_primary.vhd
bilinear_demosaic\trunk\sim\rtl_sim\work\demosaic@test\verilog.asm
bilinear_demosaic\trunk\sim\rtl_sim\work\demosaic@test\verilog.rw
bilinear_demosaic\trunk\sim\rtl_sim\work\ram@dual@port
bilinear_demosaic\trunk\sim\rtl_sim\work\ram@dual@port\_primary.dat
bilinear_demosaic\trunk\sim\rtl_sim\work\ram@dual@port\_primary.dbs
bilinear_demosaic\trunk\sim\rtl_sim\work\ram@dual@port\_primary.vhd
bilinear_demosaic\trunk\sim\rtl_sim\work\ram@dual@port\verilog.asm
bilinear_demosaic\trunk\sim\rtl_sim\work\ram@dual@port\verilog.rw
bilinear_demosaic\trunk\sim\rtl_sim\work\ram@fifo
bilinear_demosaic\trunk\sim\rtl_sim\work\ram@fifo\_primary.dat

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