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源码 基于XILINX FPGA的ofdm通信系统基带设计

  • Category : matlab
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  • Update : 2018-03-08
  • Size : 3.59mb
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  • Author :Oliv****
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Experiment of digital signal processing: parallel filtering experiment code. I hope it will help.
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FilenameSizeUpdate
Receiver\CFO_Correction.rar 412206 2015-03-01
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Receiver\Deinterleaver.rar 170899 2015-03-01
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Receiver\Frame_Detection.rar 282684 2015-03-01
Receiver\Phase_Tracking.rar 193302 2015-03-01
Receiver\QAM16_Demapping.rar 153089 2015-03-01
Receiver\Sampling_Frequency_Synchronization.rar 448197 2015-03-01
Receiver\Timing_Symcronization.rar 153608 2015-03-01
Receiver\Viterbi.rar 148804 2015-03-01
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Transmitter\clock_generator\clock_generator\clock_generator.ise 261062 2015-03-01
Transmitter\clock_generator\clock_generator\clock_generator.ise_ISE_Backup 261062 2015-03-01
Transmitter\clock_generator\clock_generator\clock_generator.restore 48790 2015-03-01
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Transmitter\clock_generator\clock_generator\clock_generator_summary.html 2319 2015-03-01
Transmitter\clock_generator\clock_generator\DCM1.xaw 3690 2015-03-01
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Transmitter\data_interleaver\data_interleaver\data_interleaver.ise_ISE_Backup 294858 2015-03-01
Transmitter\data_interleaver\data_interleaver\data_interleaver.restore 49584 2015-03-01
Transmitter\data_interleaver\data_interleaver\data_interleaver.v 7043 2015-03-01
Transmitter\data_interleaver\data_interleaver\data_interleaver_summary.html 2323 2015-03-01
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Transmitter\data_interleaver\data_interleaver\rcount_1.edn 26948 2015-03-01
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