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Verilog数字系统设计

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This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design
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Verilog数字系统设计\Chapter 1\chap1counter.v 218 2003-12-12
Verilog数字系统设计\Chapter 1\Chap1CounterTester.v 288 2003-12-12
Verilog数字系统设计\Chapter 1\confn.v 324 2004-01-13
Verilog数字系统设计\Chapter 1\dlatch.v 160 2004-01-13
Verilog数字系统设计\Chapter 1\dreg.v 226 2004-01-13
Verilog数字系统设计\Chapter 1\latchtest.v 311 2004-01-14
Verilog数字系统设计\Chapter 1\parity.v 253 2004-01-13
Verilog数字系统设计\Chapter 1\srlatch.v 257 2004-01-13
Verilog数字系统设计\Chapter 2\ALU.v 352 2005-01-20
Verilog数字系统设计\Chapter 2\ALUTester.v 352 2005-01-20
Verilog数字系统设计\Chapter 2\Counter4.v 217 2005-01-20
Verilog数字系统设计\Chapter 2\Counter4Tester.v 236 2005-01-18
Verilog数字系统设计\Chapter 2\Detector110.v 521 2005-01-24
Verilog数字系统设计\Chapter 2\Detector110Tester.v 422 2005-01-24
Verilog数字系统设计\Chapter 2\flop.v 214 2005-01-24
Verilog数字系统设计\Chapter 2\FlopTester.v 262 2005-01-24
Verilog数字系统设计\Chapter 2\MultiplexerA.v 187 2005-01-17
Verilog数字系统设计\Chapter 2\MultiplexerA2to1.v 193 2005-01-17
Verilog数字系统设计\Chapter 2\MultiplexerB.v 90 2005-01-17
Verilog数字系统设计\Chapter 2\MultiplexerC.v 81 2005-01-17
Verilog数字系统设计\Chapter 2\MultiplexerD.v 130 2005-01-17
Verilog数字系统设计\Chapter 2\MultiplexerE.v 221 2005-01-17
Verilog数字系统设计\Chapter 2\MultiplexerTester.v 436 2005-01-17
Verilog数字系统设计\Chapter 2\Mux8.v 144 2005-01-18
Verilog数字系统设计\Chapter 2\Mux8Tester.v 292 2005-01-18
Verilog数字系统设计\Chapter 2\ShiftRegister.v 367 2005-01-20
Verilog数字系统设计\Chapter 2\ShiftRegisterTester.v 470 2005-01-20
Verilog数字系统设计\Chapter 2\Synchronizer.v 171 2005-01-24
Verilog数字系统设计\Chapter 2\SynchronizerTester.v 272 2005-01-24
Verilog数字系统设计\Chapter 3\Flipflop.v 265 2005-01-25
Verilog数字系统设计\Chapter 3\FlipflopAssign.v 243 2005-05-12
Verilog数字系统设计\Chapter 3\FlipflopAssignTester.v 444 2005-02-14
Verilog数字系统设计\Chapter 3\FlipflopTester.v 273 2005-01-27
Verilog数字系统设计\Chapter 3\Fulladder.v 153 2005-01-26
Verilog数字系统设计\Chapter 3\FulladderTester.v 308 2005-02-11
Verilog数字系统设计\Chapter 3\MemoryTest.v 351 2005-02-11
Verilog数字系统设计\Chapter 3\Mux2ti1TestA.v 179 2005-02-19
Verilog数字系统设计\Chapter 3\Mux2to1.v 181 2005-02-13
Verilog数字系统设计\Chapter 3\Mux2to1BTest.v 327 2005-02-19
Verilog数字系统设计\Chapter 3\Mux2to1Multiple.v 172 2005-02-13
Verilog数字系统设计\Chapter 3\Mux2to1Net.v 144 2005-02-13
Verilog数字系统设计\Chapter 3\Mux2to1TestC.v 192 2005-02-19
Verilog数字系统设计\Chapter 3\Mux2to1Tester.v 669 2005-02-13
Verilog数字系统设计\Chapter 3\NumberTest.v 926 2005-01-27
Verilog数字系统设计\Chapter 3\OperatorTest.v 926 2005-02-10
Verilog数字系统设计\Chapter 3\SignTest.v 581 2005-02-11
Verilog数字系统设计\Chapter 4\add_1bit.v 157 2005-02-20
Verilog数字系统设计\Chapter 4\add_1bit_blocking.v 227 2005-02-27
Verilog数字系统设计\Chapter 4\add_1bit_f.v 260 2005-02-25
Verilog数字系统设计\Chapter 4\add_1bit_p.v 159 2005-02-20
Verilog数字系统设计\Chapter 4\add_1bit_p2p.v 254 2005-02-20
Verilog数字系统设计\Chapter 4\add_1bit_p_named.v 198 2005-02-20
Verilog数字系统设计\Chapter 4\add_4bit.v 323 2005-02-20
Verilog数字系统设计\Chapter 4\add_4bit_gen.v 440 2005-02-21
Verilog数字系统设计\Chapter 4\add_4bit_genif.v 532 2005-02-21
Verilog数字系统设计\Chapter 4\add_4bit_p2p.v 430 2005-02-20
Verilog数字系统设计\Chapter 4\add_4bit_vec.v 209 2005-02-20
Verilog数字系统设计\Chapter 4\Anding.v 93 2005-02-18
Verilog数字系统设计\Chapter 4\AndingTest.v 266 2005-02-18
Verilog数字系统设计\Chapter 4\maj3_p.v 316 2005-02-20
Verilog数字系统设计\Chapter 4\multi_alu.v 1082 2005-02-28
Verilog数字系统设计\Chapter 4\multi_alu_test.v 431 2005-04-15
Verilog数字系统设计\Chapter 4\priority_encoder.v 424 2005-02-28
Verilog数字系统设计\Chapter 4\quad_mux2_1.v 133 2005-02-25
Verilog数字系统设计\Chapter 4\test_add_1bit_blocking.v 343 2005-02-27
Verilog数字系统设计\Chapter 4\test_add_1bit_p.v 332 2005-02-25
Verilog数字系统设计\Chapter 4\test_add_4bit.v 550 2005-02-21
Verilog数字系统设计\Chapter 4\test_maj3_p.v 574 2005-02-20
Verilog数字系统设计\Chapter 4\test_priority_encoder.v 553 2005-02-28
Verilog数字系统设计\Chapter 4\test_quad_mux2_1.v 356 2005-02-25
Verilog数字系统设计\Chapter 4\test_xor3.v 279 2005-02-27
Verilog数字系统设计\Chapter 4\TriMux.v 197 2005-02-19
Verilog数字系统设计\Chapter 4\TriMuxTest.v 280 2005-02-18
Verilog数字系统设计\Chapter 4\xor3_behavioral.v 144 2005-02-27
Verilog数字系统设计\Chapter 4\xor3_p.v 532 2005-02-20
Verilog数字系统设计\Chapter 5\counter.v 320 2005-03-18
Verilog数字系统设计\Chapter 5\d_ff.v 171 2005-03-06
Verilog数字系统设计\Chapter 5\d_ff_hold.v 466 2005-03-12
Verilog数字系统设计\Chapter 5\d_ff_setup.v 470 2005-03-12
Verilog数字系统设计\Chapter 5\d_ff_sr_Asynch.v 436 2005-03-06
Verilog数字系统设计\Chapter 5\d_ff_sr_Synch.v 406 2005-03-06
Verilog数字系统设计\Chapter 5\d_ff__setup_hold_width_period.v 459 2005-03-13
Verilog数字系统设计\Chapter 5\gray_ounter.v 487 2005-03-18
Verilog数字系统设计\Chapter 5\latch.v 202 2005-03-06
Verilog数字系统设计\Chapter 5\latch_p.v 260 2005-03-05
Verilog数字系统设计\Chapter 5\latch_w.v 174 2005-03-06
Verilog数字系统设计\Chapter 5\lfsr1.v 542 2005-03-18
Verilog数字系统设计\Chapter 5\lfsr2.v 403 2005-03-19
Verilog数字系统设计\Chapter 5\mealy.dat 40 2005-03-19
Verilog数字系统设计\Chapter 5\mealy_detector2.v 780 2005-03-19
Verilog数字系统设计\Chapter 5\mealy_detector6.v 1288 2005-03-19
Verilog数字系统设计\Chapter 5\mealy_detector7.v 494 2005-03-19
Verilog数字系统设计\Chapter 5\mem.dat 96 2005-03-18
Verilog数字系统设计\Chapter 5\Memory_2Power_M_by_N.v 416 2005-03-13
Verilog数字系统设计\Chapter 5\misr.v 289 2005-03-18
Verilog数字系统设计\Chapter 5\misrTEST.v 351 2005-04-15
Verilog数字系统设计\Chapter 5\moore_detector.v 925 2005-03-19
Verilog数字系统设计\Chapter 5\moore_detector3.v 1252 2005-03-19
Verilog数字系统设计\Chapter 5\moore_detector4.v 1269 2005-03-19
Verilog数字系统设计\Chapter 5\pla.dat 40 2005-03-16
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