The ePWM1 is set to generate the SEQ1 conversion trigger signal when the count to the register value is compared. The ADC two channel ADCINA0 and ADCINA1 complete the interruption after the conversion is completed, and the sample values of the ADC are extracted separately in the interrupt subroutine.

Filename	Size	Update
adc_soc\cc_build_Debug.log	3751	2013-12-08
adc_soc\Debug\DSP2833x_Adc.obj	112193	2013-12-08
adc_soc\Debug\DSP2833x_ADC_cal.obj	1112	2013-12-08
adc_soc\Debug\DSP2833x_CodeStartBranch.obj	1391	2013-12-08
adc_soc\Debug\DSP2833x_DefaultIsr.obj	154779	2013-12-08
adc_soc\Debug\DSP2833x_GlobalVariableDefs.obj	121824	2013-12-08
adc_soc\Debug\DSP2833x_PieCtrl.obj	112547	2013-12-08
adc_soc\Debug\DSP2833x_PieVect.obj	119451	2013-12-08
adc_soc\Debug\DSP2833x_SysCtrl.obj	117533	2013-12-08
adc_soc\Debug\DSP2833x_usDelay.obj	1123	2013-12-08
adc_soc\Debug\example24_adc_soc.map	26464	2013-12-08
adc_soc\Debug\example24_adc_soc.out	151996	2013-12-08
adc_soc\Debug\Example_2833xAdcSoc.obj	114748	2013-12-08
adc_soc\Debug.lkf	1178	2013-12-08
adc_soc\example24_adc_soc.CS_\FILE.CDX	3072	2013-12-08
adc_soc\example24_adc_soc.CS_\FILE.DBF	1454	2013-12-08
adc_soc\example24_adc_soc.CS_\FILE.FPT	2683	2013-12-08
adc_soc\example24_adc_soc.CS_\SYMBOL.CDX	324096	2013-12-08
adc_soc\example24_adc_soc.CS_\SYMBOL.DBF	239476	2013-12-08
adc_soc\example24_adc_soc.CS_\SYMBOL.FPT	410714	2013-12-08
adc_soc\example24_adc_soc.paf2	9879	2013-12-08
adc_soc\example24_adc_soc.pjt	1995	2013-06-23
adc_soc\example24_adc_soc.sbl	7757	2013-12-08
adc_soc\Example_2833xAdcSoc.c	6611	2013-12-08
adc_soc\Debug	0	2014-11-11
adc_soc\example24_adc_soc.CS_	0	2014-11-11
adc_soc	0	2014-11-11

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