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masterspiverilog

  • Category : Compress-Decompress algrithms
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  • Update : 2008-10-13
  • Size : 176.36kb
  • Downloaded :1次
  • Author :s*****
  • About : sang
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Introduction - If you have any usage issues, please Google them yourself
spi bus controller realize the FPGA Verilog source code and test
Packet file list
(Preview for download)
Packet : 43680543masterspiverilog.rar filelist
SimpleSpi\Bench\spi_slave_model.v
SimpleSpi\Bench\tst_bench_top.v
SimpleSpi\Bench\wb_master_model.v
SimpleSpi\doc\simple_spi.doc
SimpleSpi\doc\simple_spi.pdf
SimpleSpi\Rtl\fifo4.v
SimpleSpi\Rtl\simple_spi_top.v
SimpleSpi\sim\bin\Makefile.1;content-type=text%2Fplain.txt
SimpleSpi\sim\run\Makefile.1;content-type=text%2Fplain.txt
SimpleSpi\sim\run\ncsim.log
SimpleSpi\sim\run\ncvlog.log
SimpleSpi\sim\run\simvision.sv.txt
SimpleSpi\sim\run\stdout.log
SimpleSpi\sim\run\waves.do.txt
SimpleSpi\sim\bin
SimpleSpi\sim\run
SimpleSpi\Bench
SimpleSpi\doc
SimpleSpi\Rtl
SimpleSpi\sim
SimpleSpi
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