09_USB_OV7725_Gray_Sobel_Erosion MIPI Alliance Spe

09_USB_OV7725_Gray_Sobel_Erosion

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Category : USB develop
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Update : 2018-06-06
Size : 574kb
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MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2)

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Filename	Size	Update
core	0	2014-03-24
dev	0	2018-04-28
dev\CMOS_VIP_HDL_Demo.asm.rpt	8617	2014-04-01
dev\CMOS_VIP_HDL_Demo.cdf	470	2014-04-01
dev\CMOS_VIP_HDL_Demo.done	26	2014-04-01
dev\CMOS_VIP_HDL_Demo.fit.rpt	599103	2014-04-01
dev\CMOS_VIP_HDL_Demo.fit.smsg	567	2014-04-01
dev\CMOS_VIP_HDL_Demo.fit.summary	638	2014-04-01
dev\CMOS_VIP_HDL_Demo.flow.rpt	8007	2014-04-01
dev\CMOS_VIP_HDL_Demo.jdi	236	2014-04-01
dev\CMOS_VIP_HDL_Demo.map.rpt	285085	2014-04-01
dev\CMOS_VIP_HDL_Demo.map.smsg	160	2014-04-01
dev\CMOS_VIP_HDL_Demo.map.summary	497	2014-04-01
dev\CMOS_VIP_HDL_Demo.pin	20259	2014-04-01
dev\CMOS_VIP_HDL_Demo.qpf	1328	2014-03-17
dev\CMOS_VIP_HDL_Demo.qsf	6347	2014-04-01
dev\CMOS_VIP_HDL_Demo.qws	2692	2014-04-01
dev\CMOS_VIP_HDL_Demo.sof	358655	2014-04-01
dev\CMOS_VIP_HDL_Demo.sta.rpt	1531201	2014-04-01
dev\CMOS_VIP_HDL_Demo.sta.summary	4402	2014-04-01
dev\CMOS_VIP_RGB888_YCbCr444.map	189	2014-03-17
dev\PLLJ_PLLSPE_INFO.txt	166	2014-04-01
dev\USB_OV7725_Gray_Sobe_Erosion.map	189	2014-03-20
dev\USB_OV7725_Gray_Sobe_Erosionl.map	189	2014-03-20
dev\USB_OV7725_Gray_Sobel.map	189	2014-03-19
dev\USB_OV7725_Gray_Sobel_Erosion.jic	524511	2014-04-01
dev\USB_OV7725_Gray_Sobel_Erosion.map	189	2014-04-01
dev\USB_OV7725_RGB2Gray.map	189	2014-03-18
dev\USB_OV7725_YCbCr2Gray.map	189	2014-03-19
dev\VIP_System.sdc	2448	2014-03-16
doc	0	2013-11-08
sim	0	2018-04-28
sim\Video_Image_Processor_TB	0	2018-04-28
sim\Video_Image_Processor_TB\__Previews	0	2018-04-28
sim\Video_Image_Processor_TB\__Previews\Video_Image_Processor_TB.vPreview	95451	2014-03-20
sim\Video_Image_Processor_TB\CMOS_Capture_RGB565.v	6577	2014-03-16
sim\Video_Image_Processor_TB\Line_Shift_RAM_1Bit.v	5568	2014-03-20
sim\Video_Image_Processor_TB\Line_Shift_RAM_8Bit.v	5133	2014-03-19
sim\Video_Image_Processor_TB\Sobel_Threshold_Adj.v	2950	2014-03-19
sim\Video_Image_Processor_TB\SQRT.v	3501	2013-05-26
sim\Video_Image_Processor_TB\transcript	6609	2014-03-20
sim\Video_Image_Processor_TB\Video_Image_Processor.v	5014	2014-03-20
sim\Video_Image_Processor_TB\Video_Image_Processor_TB.cr.mti	6593	2014-03-20
sim\Video_Image_Processor_TB\Video_Image_Processor_TB.mpf	27678	2014-03-20
sim\Video_Image_Processor_TB\Video_Image_Processor_TB.v	6553	2014-03-19
sim\Video_Image_Processor_TB\Video_Image_Simulate_CMOS.v	6362	2014-03-16
sim\Video_Image_Processor_TB\VIP_Bit_Erosion_Detector.v	6328	2014-03-20
sim\Video_Image_Processor_TB\VIP_Matrix_Generate_3X3_1Bit.v	6858	2014-03-29
sim\Video_Image_Processor_TB\VIP_Matrix_Generate_3X3_8Bit.v	6871	2014-03-19
sim\Video_Image_Processor_TB\VIP_Sobel_Edge_Detector.v	7803	2014-03-29
sim\Video_Image_Processor_TB\vsim.wlf	237568	2014-03-20
sim\Video_Image_Processor_TB\wave.do	3696	2014-03-20
sim\Video_Image_Processor_TB\work	0	2018-04-28
sim\Video_Image_Processor_TB\work\@c@m@o@s_@capture_@r@g@b565	0	2018-04-28
sim\Video_Image_Processor_TB\work\@c@m@o@s_@capture_@r@g@b565\_primary.dat	2574	2014-03-20
sim\Video_Image_Processor_TB\work\@c@m@o@s_@capture_@r@g@b565\_primary.dbs	3281	2014-03-20
sim\Video_Image_Processor_TB\work\@c@m@o@s_@capture_@r@g@b565\_primary.vhd	906	2014-03-20
sim\Video_Image_Processor_TB\work\@c@m@o@s_@capture_@r@g@b565\verilog.prw	1785	2014-03-20
sim\Video_Image_Processor_TB\work\@c@m@o@s_@capture_@r@g@b565\verilog.psm	26400	2014-03-20
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_1@bit	0	2018-04-28
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_1@bit\_primary.dat	1413	2014-03-20
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_1@bit\_primary.dbs	1239	2014-03-20
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_1@bit\_primary.vhd	690	2014-03-20
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_1@bit\verilog.prw	505	2014-03-20
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_1@bit\verilog.psm	9056	2014-03-20
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_8@bit	0	2018-04-28
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_8@bit\_primary.dat	1413	2014-03-20
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_8@bit\_primary.dbs	1239	2014-03-20
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_8@bit\_primary.vhd	690	2014-03-20
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_8@bit\verilog.prw	517	2014-03-20
sim\Video_Image_Processor_TB\work\@line_@shift_@r@a@m_8@bit\verilog.psm	9336	2014-03-20
sim\Video_Image_Processor_TB\work\@s@q@r@t	0	2018-04-28
sim\Video_Image_Processor_TB\work\@s@q@r@t\_primary.dat	895	2014-03-20
sim\Video_Image_Processor_TB\work\@s@q@r@t\_primary.dbs	804	2014-03-20
sim\Video_Image_Processor_TB\work\@s@q@r@t\_primary.vhd	273	2014-03-20
sim\Video_Image_Processor_TB\work\@s@q@r@t\verilog.prw	263	2014-03-20
sim\Video_Image_Processor_TB\work\@s@q@r@t\verilog.psm	5264	2014-03-20
sim\Video_Image_Processor_TB\work\@sobel_@threshold_@adj	0	2018-04-28
sim\Video_Image_Processor_TB\work\@sobel_@threshold_@adj\_primary.dat	1413	2014-03-20
sim\Video_Image_Processor_TB\work\@sobel_@threshold_@adj\_primary.dbs	1184	2014-03-20
sim\Video_Image_Processor_TB\work\@sobel_@threshold_@adj\_primary.vhd	429	2014-03-20
sim\Video_Image_Processor_TB\work\@sobel_@threshold_@adj\verilog.prw	417	2014-03-20
sim\Video_Image_Processor_TB\work\@sobel_@threshold_@adj\verilog.psm	10272	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@bit_@erosion_@detector	0	2018-04-28
sim\Video_Image_Processor_TB\work\@v@i@p_@bit_@erosion_@detector\_primary.dat	2163	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@bit_@erosion_@detector\_primary.dbs	2855	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@bit_@erosion_@detector\_primary.vhd	970	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@bit_@erosion_@detector\verilog.prw	1331	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@bit_@erosion_@detector\verilog.psm	18680	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@matrix_@generate_3@x3_1@bit	0	2018-04-28
sim\Video_Image_Processor_TB\work\@v@i@p_@matrix_@generate_3@x3_1@bit\_primary.dat	2354	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@matrix_@generate_3@x3_1@bit\_primary.dbs	2359	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@matrix_@generate_3@x3_1@bit\_primary.vhd	1327	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@matrix_@generate_3@x3_1@bit\verilog.prw	1764	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@matrix_@generate_3@x3_1@bit\verilog.psm	31552	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@matrix_@generate_3@x3_8@bit	0	2018-04-28
sim\Video_Image_Processor_TB\work\@v@i@p_@matrix_@generate_3@x3_8@bit\_primary.dat	2652	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@matrix_@generate_3@x3_8@bit\_primary.dbs	2603	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@matrix_@generate_3@x3_8@bit\_primary.vhd	1517	2014-03-20
sim\Video_Image_Processor_TB\work\@v@i@p_@matrix_@generate_3@x3_8@bit\verilog.prw	2019	2014-03-20

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