SH3, based SH7709S chips, the use of assembly language instructions generated TRAPA trap abnormal conditions, call the blinking LED procedure. Flashing LEDs to control the use of cycle time delay, the law of custom.

Packet : 5956451trap_2.rar filelist
trap_2\trap_2\7709A.H
trap_2\trap_2\7709S.H
trap_2\trap_2\Assemblyincludefile.shl
trap_2\trap_2\Assemblylistfile.shl
trap_2\trap_2\Assemblysourcefile.shl
trap_2\trap_2\C++headerfile.shl
trap_2\trap_2\C++listfile.shl
trap_2\trap_2\C++sourcefile.shl
trap_2\trap_2\Cheaderfile.shl
trap_2\trap_2\Clistfile.shl
trap_2\trap_2\Csourcefile.shl
trap_2\trap_2\dbsct.c
trap_2\trap_2\Debug
trap_2\trap_2\Default.shl
trap_2\trap_2\defaultsession.hsf
trap_2\trap_2\editordefault.shl
trap_2\trap_2\env.inc
trap_2\trap_2\Expandedassemblysourcefile.shl
trap_2\trap_2\Hexfile.shl
trap_2\trap_2\intprg.src
trap_2\trap_2\iodefine.h
trap_2\trap_2\Libraryinformationfile.shl
trap_2\trap_2\Linkagemapfile.shl
trap_2\trap_2\Linkagesymbolfile.shl
trap_2\trap_2\PreprocessedC++sourcefile.shl
trap_2\trap_2\PreprocessedCsourcefile.shl
trap_2\trap_2\Readme.txt
trap_2\trap_2\Release
trap_2\trap_2\resetprg.c
trap_2\trap_2\S-Recordfile.shl
trap_2\trap_2\sbrk.c
trap_2\trap_2\sbrk.h
trap_2\trap_2\SimDebug_SH-3\dbsct.obj
trap_2\trap_2\SimDebug_SH-3\dbsct.shc
trap_2\trap_2\SimDebug_SH-3\intprg.obj
trap_2\trap_2\SimDebug_SH-3\intprg.sha
trap_2\trap_2\SimDebug_SH-3\resetprg.obj
trap_2\trap_2\SimDebug_SH-3\resetprg.shc
trap_2\trap_2\SimDebug_SH-3\sbrk.obj
trap_2\trap_2\SimDebug_SH-3\sbrk.shc
trap_2\trap_2\SimDebug_SH-3\SimDebug_SH-3.hdp
trap_2\trap_2\SimDebug_SH-3\trap_2.abs
trap_2\trap_2\SimDebug_SH-3\trap_2.hlk
trap_2\trap_2\SimDebug_SH-3\trap_2.lib
trap_2\trap_2\SimDebug_SH-3\trap_2.map
trap_2\trap_2\SimDebug_SH-3\trap_2.mot
trap_2\trap_2\SimDebug_SH-3\trap_2.obj
trap_2\trap_2\SimDebug_SH-3\trap_2.shc
trap_2\trap_2\SimDebug_SH-3\trap_2.shg
trap_2\trap_2\SimDebug_SH-3\vecttbl.obj
trap_2\trap_2\SimDebug_SH-3\vecttbl.sha
trap_2\trap_2\SimDebug_SH-3\vhandler.obj
trap_2\trap_2\SimDebug_SH-3\vhandler.sha
trap_2\trap_2\SimDebug_SH-3
trap_2\trap_2\simsessionsh-3.hsf
trap_2\trap_2\stacksct.h
trap_2\trap_2\trap_2.c
trap_2\trap_2\trap_2.hwp
trap_2\trap_2\trap_2.pgs
trap_2\trap_2\trap_2.tps
trap_2\trap_2\vect.inc
trap_2\trap_2\vecttbl.src
trap_2\trap_2\vhandler.src
trap_2\trap_2
trap_2\trap_2.Hbp
trap_2\trap_2.hws
trap_2\trap_2.tws
trap_2

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