Packet : 93317480cisc8bitcpu.rar filelist
cisc8bit
cisc8bit\work
cisc8bit\work\u@p@c
cisc8bit\work\u@i@r
cisc8bit\work\temp
cisc8bit\work\shifter
cisc8bit\work\setpcw
cisc8bit\work\register
cisc8bit\work\reg@r@agen
cisc8bit\work\mem
cisc8bit\work\glbl
cisc8bit\work\cpu
cisc8bit\work\clkgen
cisc8bit\work\buffer
cisc8bit\work\@p@cin_gen
cisc8bit\work\@p@c
cisc8bit\work\@m@agen
cisc8bit\work\@l@b
cisc8bit\work\@c@p@utest
cisc8bit\work\@c@m
cisc8bit\work\@a@l@u
cisc8bit\xst
cisc8bit\xst\work
cisc8bit\xst\work\vlg79
cisc8bit\xst\work\vlg60
cisc8bit\xst\work\vlg5E
cisc8bit\xst\work\vlg53
cisc8bit\xst\work\vlg50
cisc8bit\xst\work\vlg4F
cisc8bit\xst\work\vlg40
cisc8bit\xst\work\vlg3E
cisc8bit\xst\work\vlg30
cisc8bit\xst\work\vlg2C
cisc8bit\xst\work\vlg2A
cisc8bit\xst\work\vlg29
cisc8bit\xst\work\vlg24
cisc8bit\xst\work\vlg1E
cisc8bit\xst\work\vlg1C
cisc8bit\xst\work\vlg12
cisc8bit\xst\work\vlg0F
cisc8bit\xst\work\vlg0B
cisc8bit\xst\work\sub00
cisc8bit\_ngo
cisc8bit\_tmp_
cisc8bit\_tmp_\coretmpdir
cisc8bit\__projnav
cisc8bit\.untf
cisc8bit\ALU.bld
cisc8bit\ALU.cmd_log
cisc8bit\ALU.ngc
cisc8bit\ALU.ngr
cisc8bit\ALU.prj
cisc8bit\ALU.spl
cisc8bit\ALU.sprj
cisc8bit\ALU.stx
cisc8bit\alu.sym
cisc8bit\ALU.syr
cisc8bit\ALU.v
cisc8bit\automake.log
cisc8bit\bitgen.ut
cisc8bit\buffer.spl
cisc8bit\buffer.sym
cisc8bit\buffer.v
cisc8bit\clkgen'.v
cisc8bit\clkgen.bgn
cisc8bit\clkgen.bit
cisc8bit\clkgen.bld
cisc8bit\clkgen.cmd_log
cisc8bit\clkgen.drc
cisc8bit\clkgen.ldo
cisc8bit\clkgen.lso
cisc8bit\clkgen.mrp
cisc8bit\clkgen.nc1
cisc8bit\clkgen.ncd
cisc8bit\clkgen.ngc
cisc8bit\clkgen.ngd
cisc8bit\clkgen.ngm
cisc8bit\clkgen.ngr
cisc8bit\clkgen.pad
cisc8bit\clkgen.pad_txt
cisc8bit\clkgen.par
cisc8bit\clkgen.pcf
cisc8bit\clkgen.placed_ncd_tracker
cisc8bit\clkgen.prj
cisc8bit\clkgen.routed_ncd_tracker
cisc8bit\clkgen.stx
cisc8bit\clkgen.syr
cisc8bit\clkgen.twr
cisc8bit\clkgen.twx
cisc8bit\clkgen.ut
cisc8bit\clkgen.v
cisc8bit\clkgen.xpi
cisc8bit\clkgen_last_par.ncd
cisc8bit\clkgen_map.ncd
cisc8bit\clkgen_map.ngm
cisc8bit\clkgen_new.bgn
cisc8bit\clkgen_new.bit
cisc8bit\clkgen_new.bld
cisc8bit\clkgen_new.cmd_log
cisc8bit\clkgen_new.dly
cisc8bit\clkgen_new.drc
cisc8bit\clkgen_new.mrp
cisc8bit\clkgen_new.nc1
cisc8bit\clkgen_new.ncd
cisc8bit\clkgen_new.ngc
cisc8bit\clkgen_new.ngd
cisc8bit\clkgen_new.ngm
cisc8bit\clkgen_new.ngr
cisc8bit\clkgen_new.pad
cisc8bit\clkgen_new.par
cisc8bit\clkgen_new.pcf
cisc8bit\clkgen_new.prj
cisc8bit\clkgen_new.sprj
cisc8bit\clkgen_new.stx
cisc8bit\clkgen_new.syr
cisc8bit\clkgen_new.twr
cisc8bit\clkgen_new.twx
cisc8bit\clkgen_new.ut
cisc8bit\clkgen_new.v
cisc8bit\clkgen_new.xpi
cisc8bit\clkgen_new_map.ncd
cisc8bit\clkgen_new_map.ngm
cisc8bit\clkgen_new_ngdbuild.nav
cisc8bit\clkgen_pad.csv
cisc8bit\clkgen_pad.txt
cisc8bit\clkgen_test.v
cisc8bit\clkgen_vhdl.prj
cisc8bit\cm.mic
cisc8bit\cm.v
cisc8bit\CMprogram
cisc8bit\coregen.log
cisc8bit\coregen.prj
cisc8bit\cpu.cmd_log
cisc8bit\cpu.dly
cisc8bit\cpu.ldo
cisc8bit\cpu.lso
cisc8bit\cpu.ngm
cisc8bit\cpu.npl
cisc8bit\cpu.pad_txt
cisc8bit\cpu.prj
cisc8bit\cpu.sprj
cisc8bit\cpu.syr
cisc8bit\cpu.ut
cisc8bit\cpu.versim_xlate
cisc8bit\cpu.xlate_nlf
cisc8bit\CPUtest.cmd_log
cisc8bit\CPUtest.ldo
cisc8bit\CPUtest.lso
cisc8bit\CPUtest.prj
cisc8bit\CPUtest.spl
cisc8bit\CPUtest.sprj
cisc8bit\cputest.sym
cisc8bit\CPUtest.syr
cisc8bit\CPUtest.v
cisc8bit\cpu_last_par.ncd
cisc8bit\cpu_ngdbuild.nav
cisc8bit\cpu_translate.nlf
cisc8bit\cpu_translate.v
cisc8bit\LA.v
cisc8bit\LB.v
cisc8bit\MAgen.v
cisc8bit\PC.v
cisc8bit\PCin_gen.v
cisc8bit\pins_assign.ucf.bak
cisc8bit\pins_assign.ucf.untf
cisc8bit\register.v
cisc8bit\regRAgen.v
cisc8bit\rom.v
cisc8bit\sequencer.vhd
cisc8bit\setpcw.v
cisc8bit\shifter.v
cisc8bit\shift_test.v
cisc8bit\test
cisc8bit\test.v
cisc8bit\test2.cfg
cisc8bit\testprogram
cisc8bit\transcript
cisc8bit\uIR.v.bak
cisc8bit\uPC.v
cisc8bit\userlang.tpl
cisc8bit\vsim.wlf
cisc8bit\work\_info
cisc8bit\work\u@p@c\verilog.asm
cisc8bit\work\u@p@c\_primary.dat
cisc8bit\work\u@p@c\_primary.vhd
cisc8bit\work\u@i@r\verilog.asm
cisc8bit\work\u@i@r\_primary.dat
cisc8bit\work\u@i@r\_primary.vhd
cisc8bit\work\temp\verilog.asm
cisc8bit\work\temp\_primary.dat
cisc8bit\work\temp\_primary.vhd
cisc8bit\work\shifter\verilog.asm
cisc8bit\work\shifter\_primary.dat
cisc8bit\work\shifter\_primary.vhd
cisc8bit\work\setpcw\verilog.asm
cisc8bit\work\setpcw\_primary.dat
cisc8bit\work\setpcw\_primary.vhd
cisc8bit\work\register\verilog.asm
cisc8bit\work\register\_primary.dat
cisc8bit\work\register\_primary.vhd
cisc8bit\work\reg@r@agen\verilog.asm
cisc8bit\work\reg@r@agen\_primary.dat
cisc8bit\work\reg@r@agen\_primary.vhd
cisc8bit\work\mem\verilog.asm
cisc8bit\work\mem\_primary.dat
cisc8bit\work\mem\_primary.vhd
cisc8bit\work\glbl\verilog.asm
cisc8bit\work\glbl\_primary.dat
cisc8bit\work\glbl\_primary.vhd
cisc8bit\work\cpu\verilog.asm
cisc8bit\work\cpu\_primary.dat
cisc8bit\work\cpu\_primary.vhd
cisc8bit\work\clkgen\verilog.asm
cisc8bit\work\clkgen\_primary.dat
cisc8bit\work\clkgen\_primary.vhd
cisc8bit\work\buffer\verilog.asm
cisc8bit\work\buffer\_primary.dat
cisc8bit\work\buffer\_primary.vhd
cisc8bit\work\@p@cin_gen\verilog.asm
cisc8bit\work\@p@cin_gen\_primary.dat
cisc8bit\work\@p@cin_gen\_primary.vhd
cisc8bit\work\@p@c\verilog.asm
cisc8bit\work\@p@c\_primary.dat
cisc8bit\work\@p@c\_primary.vhd
cisc8bit\work\@m@agen\verilog.asm
cisc8bit\work\@m@agen\_primary.dat
cisc8bit\work\@m@agen\_primary.vhd
cisc8bit\work\@l@b\verilog.asm
cisc8bit\work\@l@b\_primary.dat
cisc8bit\work\@l@b\_primary.vhd
cisc8bit\work\@c@p@utest\verilog.asm
cisc8bit\work\@c@p@utest\_primary.dat
cisc8bit\work\@c@p@utest\_primary.vhd
cisc8bit\work\@c@m\verilog.asm
cisc8bit\work\@c@m\_primary.dat
cisc8bit\work\@c@m\_primary.vhd
cisc8bit\work\@a@l@u\verilog.asm
cisc8bit\work\@a@l@u\_primary.dat
cisc8bit\work\@a@l@u\_primary.vhd
cisc8bit\x.cfg
cisc8bit\xst\work\hdllib.ref
cisc8bit\xst\work\vlg79\shifter.bin
cisc8bit\xst\work\vlg60\clkgen.bin
cisc8bit\xst\work\vlg5E\setpcw.bin
cisc8bit\xst\work\vlg5E\DeviceStateRegister.bin
cisc8bit\xst\work\vlg53\PC.bin
cisc8bit\xst\work\vlg50\cpu.bin
cisc8bit\xst\work\vlg4F\regRAgen.bin
cisc8bit\xst\work\vlg40\uPC.bin
cisc8bit\xst\work\vlg3E\LB.bin
cisc8bit\xst\work\vlg30\MAgen.bin
cisc8bit\xst\work\vlg2C\uIR.bin
cisc8bit\xst\work\vlg2A\ALU.bin
cisc8bit\xst\work\vlg29\register.bin
cisc8bit\xst\work\vlg24\CPUtest.bin
cisc8bit\xst\work\vlg1E\buffer.bin
cisc8bit\xst\work\vlg1C\CM.bin
cisc8bit\xst\work\vlg12\temp.bin
cisc8bit\xst\work\vlg0F\PCin_gen.bin
cisc8bit\xst\work\vlg0B\mem.bin
cisc8bit\xst\work\sub00\vhpl00.vho
cisc8bit\xst\work\sub00\vhpl01.vho
cisc8bit\xst\work\hdpdeps.ref
cisc8bit\_impact.cmd
cisc8bit\_impact.log
cisc8bit\_ngo\netlist.lst
cisc8bit\__projnav\ALU.xst
cisc8bit\__projnav\ALU._prj
cisc8bit\__projnav\ALU._sprj
cisc8bit\__projnav\ALU_jhdparse_tcl.rsp
cisc8bit\__projnav\bitgen.rsp
cisc8bit\__projnav\buffer_jhdparse_tcl.rsp
cisc8bit\__projnav\clkgen.xst
cisc8bit\__projnav\clkgen_jhdparse_tcl.rsp
cisc8bit\__projnav\clkgen_ncdTOut_tcl.rsp
cisc8bit\__projnav\clkgen_new.xst
cisc8bit\__projnav\clkgen_new._prj
cisc8bit\__projnav\clkgen_new._sprj
cisc8bit\__projnav\clkgen_new_jhdparse_tcl.rsp
cisc8bit\__projnav\clkgen_new_ncdTOut_tcl.rsp
cisc8bit\__projnav\cm_jhdparse_tcl.rsp
cisc8bit\__projnav\coregen.rsp
cisc8bit\__projnav\cpu.gfl
cisc8bit\__projnav\cpu.xst
cisc8bit\__projnav\cpu._prj
cisc8bit\__projnav\cpu._sprj
cisc8bit\__projnav\cpu8bitv.gfl
cisc8bit\__projnav\cpu8bitv_flowplus.gfl
cisc8bit\__projnav\CPUtest.xst
cisc8bit\__projnav\CPUtest._prj
cisc8bit\__projnav\CPUtest._sprj
cisc8bit\__projnav\CPUtest_jhdparse_tcl.rsp
cisc8bit\__projnav\CPUtest_ncdTOut_tcl.rsp
cisc8bit\__projnav\cpu_flowplus.gfl
cisc8bit\__projnav\CPU_jhdparse_tcl.rsp
cisc8bit\__projnav\cpu_ncdTOut_tcl.rsp
cisc8bit\__projnav\ednTOngd_tcl.rsp
cisc8bit\__projnav\jhdparse.log
cisc8bit\__projnav\LA_jhdparse_tcl.rsp
cisc8bit\__projnav\LB_jhdparse_tcl.rsp
cisc8bit\__projnav\MAgen_jhdparse_tcl.rsp
cisc8bit\__projnav\nc1TOncd_tcl.rsp
cisc8bit\__projnav\parentEditConstraintsTextApp_tcl.rsp
cisc8bit\__projnav\PCin_gen_jhdparse_tcl.rsp
cisc8bit\__projnav\PC_jhdparse_tcl.rsp
cisc8bit\__projnav\posttrc.log
cisc8bit\__projnav\register_jhdparse_tcl.rsp
cisc8bit\__projnav\regRAgen_jhdparse_tcl.rsp
cisc8bit\__projnav\rom_jhdparse_tcl.rsp
cisc8bit\__projnav\runXst_tcl.rsp
cisc8bit\__projnav\setpcw_jhdparse_tcl.rsp
cisc8bit\__projnav\shifter_jhdparse_tcl.rsp
cisc8bit\__projnav\uIR_jhdparse_tcl.rsp
cisc8bit\__projnav\uPC_jhdparse_tcl.rsp
cisc8bit\__projnav\vTOldo_tcl.rsp
cisc8bit\__projnav\map.log
cisc8bit\__projnav\par.log
cisc8bit\__projnav.log
cisc8bit\实验计算机的硬件设计.doc
cisc8bit\课程设计教师参考资料加附录.doc
cisc8bit\DSR.v.bak
cisc8bit\DSR.v
cisc8bit\uIR.v
cisc8bit\CPU.v.bak
cisc8bit\CPU.v
cisc8bit\pins_assign.ucf
cisc8bit\cpu.stx
cisc8bit\cpu.ngr
cisc8bit\cpu.ngc
cisc8bit\cpu.bld
cisc8bit\cpu.ngd
cisc8bit\cpu.mrp
cisc8bit\cpu_map.ngm
cisc8bit\cpu_map.ncd
cisc8bit\cpu.pcf
cisc8bit\cpu.nc1
cisc8bit\cpu.par
cisc8bit\cpu_pad.csv
cisc8bit\cpu.pad
cisc8bit\cpu_pad.txt
cisc8bit\cpu.ncd
cisc8bit\cpu.xpi
cisc8bit\cpu.placed_ncd_tracker
cisc8bit\cpu.routed_ncd_tracker
cisc8bit\cpu.twx
cisc8bit\cpu.twr
cisc8bit\cpu.bgn
cisc8bit\cpu.drc
cisc8bit\cpu.bit
cisc8bit\cpu.dhp
cisc8bit\04年课程设计指导书8位机.doc

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