Packet : 244756verilog源码13.rar filelist
Gate_reduce
Gate_reduce\Verilog
Gate_reduce\Verilog\Synopsys_dw
Gate_reduce\Verilog\Synopsys_dw\gate_reduce.v
Gate_reduce\Verilog\Synopsys_dw\M1_files
Gate_reduce\Verilog\Synopsys_dw\M1_files\time_sim.v
Gate_reduce\Verilog\Synopsys_dw\xilinx_dw.v
Gate_reduce\Verilog\Xilinx_dw
Gate_reduce\Verilog\Xilinx_dw\gate_reduce.v
Gate_reduce\Verilog\Xilinx_dw\M1_files
Gate_reduce\Verilog\Xilinx_dw\M1_files\time_sim.v
Gate_reduce\Verilog\Xilinx_dw\xilinx_dw.v

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