Packet : 1092012688051core-verilog.rar filelist
8051core-Verilog\8051IPcore_readme.mht
8051core-Verilog\Acc.v
8051core-Verilog\All.v
8051core-Verilog\Alu.v
8051core-Verilog\alu_src1_sel.v
8051core-Verilog\alu_src2_sel.v
8051core-Verilog\alu_src3_sel.v
8051core-Verilog\Comp.v
8051core-Verilog\cy_select.v
8051core-Verilog\Decoder.v
8051core-Verilog\Defines.v
8051core-Verilog\Divide.v
8051core-Verilog\Dptr.v
8051core-Verilog\ext_addr_sel.v
8051core-Verilog\immediate_sel.v
8051core-Verilog\IndiAddr.v
8051core-Verilog\Make
8051core-Verilog\mc8051_overview.pdf
8051core-Verilog\mc8051_ug.pdf
8051core-Verilog\Multiply.v
8051core-Verilog\op_select.v
8051core-Verilog\Pc.v
8051core-Verilog\Port_out.v
8051core-Verilog\Psw.v
8051core-Verilog\Ram.v
8051core-Verilog\ram_rd_sel.v
8051core-Verilog\Ram_sel.v
8051core-Verilog\ram_wr_sel.v
8051core-Verilog\Reg1.v
8051core-Verilog\Reg2.v
8051core-Verilog\Reg3.v
8051core-Verilog\Reg4.v
8051core-Verilog\Reg5.v
8051core-Verilog\Reg8.v
8051core-Verilog\Reg8r.v
8051core-Verilog\Rom.v
8051core-Verilog\rom_addr_sel.v
8051core-Verilog\Sp.v
8051core-Verilog\Tb_all.v
8051core-Verilog\transcript
8051core-Verilog

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