Introduction - If you have any usage issues, please Google them yourself
UART interface of the VHDL source code, successfully applied in the development of SOC projects, not for commercial purposes.
Packet : 31767663uart_serial.rar filelist
uart_serial\CVS\Entries
uart_serial\CVS\Entries.Extra
uart_serial\CVS\Entries.Extra.Old
uart_serial\CVS\Entries.Old
uart_serial\CVS\Repository
uart_serial\CVS\Root
uart_serial\CVS\Template
uart_serial\modelsim\compile.tcl
uart_serial\modelsim\CVS\Entries
uart_serial\modelsim\CVS\Entries.Extra
uart_serial\modelsim\CVS\Entries.Extra.Old
uart_serial\modelsim\CVS\Entries.Old
uart_serial\modelsim\CVS\Repository
uart_serial\modelsim\CVS\Root
uart_serial\modelsim\CVS\Template
uart_serial\modelsim\run.tcl
uart_serial\modelsim\uart.mpf
uart_serial\modelsim\wave.do
uart_serial\sources\CVS\Entries
uart_serial\sources\CVS\Entries.Extra
uart_serial\sources\CVS\Entries.Extra.Old
uart_serial\sources\CVS\Entries.Old
uart_serial\sources\CVS\Repository
uart_serial\sources\CVS\Root
uart_serial\sources\CVS\Template
uart_serial\sources\uart_serial.vhd
uart_serial\testbench\CVS\Entries
uart_serial\testbench\CVS\Entries.Extra
uart_serial\testbench\CVS\Entries.Extra.Old
uart_serial\testbench\CVS\Entries.Old
uart_serial\testbench\CVS\Repository
uart_serial\testbench\CVS\Root
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uart_serial\testbench\tb_uart.vhd
uart_serial\modelsim\CVS
uart_serial\sources\CVS
uart_serial\testbench\CVS
uart_serial\CVS
uart_serial\modelsim
uart_serial\sources
uart_serial\testbench
uart_serial