Introduction - If you have any usage issues, please Google them yourself
Written in fairly good USBPHY source code has been validated.
Packet : 51622436usb_phy.rar filelist
usb_phy\CVS\Entries
usb_phy\CVS\Entries.Extra
usb_phy\CVS\Entries.Extra.Old
usb_phy\CVS\Entries.Old
usb_phy\CVS\Repository
usb_phy\CVS\Root
usb_phy\CVS\Template
usb_phy\doc\CVS\Entries
usb_phy\doc\CVS\Entries.Extra
usb_phy\doc\CVS\Entries.Extra.Old
usb_phy\doc\CVS\Entries.Old
usb_phy\doc\CVS\Repository
usb_phy\doc\CVS\Root
usb_phy\doc\CVS\Template
usb_phy\doc\README.txt
usb_phy\rtl\CVS\Entries
usb_phy\rtl\CVS\Entries.Extra
usb_phy\rtl\CVS\Entries.Extra.Old
usb_phy\rtl\CVS\Entries.Old
usb_phy\rtl\CVS\Repository
usb_phy\rtl\CVS\Root
usb_phy\rtl\CVS\Template
usb_phy\rtl\verilog\CVS\Entries
usb_phy\rtl\verilog\CVS\Entries.Extra
usb_phy\rtl\verilog\CVS\Entries.Extra.Old
usb_phy\rtl\verilog\CVS\Entries.Old
usb_phy\rtl\verilog\CVS\Repository
usb_phy\rtl\verilog\CVS\Root
usb_phy\rtl\verilog\CVS\Template
usb_phy\rtl\verilog\timescale.v
usb_phy\rtl\verilog\usb_phy.v
usb_phy\rtl\verilog\usb_rx_phy.v
usb_phy\rtl\verilog\usb_tx_phy.v
usb_phy\rtl\verilog\CVS
usb_phy\doc\CVS
usb_phy\rtl\CVS
usb_phy\rtl\verilog
usb_phy\CVS
usb_phy\doc
usb_phy\rtl
usb_phy