MSP-FET430P410 Demo- Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLKDescription Toggle P5.1 using using software and TA_0 ISR. Toggle rate is set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK. Durring the TA_0 ISR P5.1 is toggled and 50000 clock cycles are added to CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off andused only durring TA_ISR. ACLK = n/a, MCLK = SMCLK = TACLK = DCO ~ 800k

Packet : 45666015fet410_ta.rar filelist
fet410_ta.c

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