In the UP3 development board has been verified VHDL code. Accurate to one-tenth of seconds, with the alarm clock, the whole point timekeeping, time and other functions can be re-instated in the LCD1602 display. Absolutely recommended online than other similar features to the entire code and verified. Most crucial point is that the code is directly through the I2C bus to obtain the UP3 development board real time clock chip time, of course, can also I2C clock chip on the set.

Packet : 11912873up3_rtc_clock.rar filelist
实验5-时钟设计-最终版\UP3_CLOCK.asm.rpt
实验5-时钟设计-最终版\UP3_CLOCK.cdf
实验5-时钟设计-最终版\UP3_CLOCK.done
实验5-时钟设计-最终版\UP3_CLOCK.dpf
实验5-时钟设计-最终版\UP3_CLOCK.fit.rpt
实验5-时钟设计-最终版\UP3_CLOCK.fit.smsg
实验5-时钟设计-最终版\UP3_CLOCK.fit.summary
实验5-时钟设计-最终版\UP3_CLOCK.flow.rpt
实验5-时钟设计-最终版\UP3_CLOCK.map.rpt
实验5-时钟设计-最终版\UP3_CLOCK.map.summary
实验5-时钟设计-最终版\UP3_CLOCK.pin
实验5-时钟设计-最终版\UP3_CLOCK.pof
实验5-时钟设计-最终版\UP3_CLOCK.qpf
实验5-时钟设计-最终版\UP3_CLOCK.qsf
实验5-时钟设计-最终版\UP3_CLOCK.qws
实验5-时钟设计-最终版\UP3_CLOCK.sim.rpt
实验5-时钟设计-最终版\UP3_CLOCK.sof
实验5-时钟设计-最终版\UP3_CLOCK.tan.rpt
实验5-时钟设计-最终版\UP3_CLOCK.tan.summary
实验5-时钟设计-最终版\UP3_CLOCK.vhd
实验5-时钟设计-最终版\UP3_CLOCK.vwf
实验5-时钟设计-最终版\UP3_CLOCK_assignment_defaults.qdf
实验5-时钟设计-最终版\db\add_sub_4rh.tdf
实验5-时钟设计-最终版\db\add_sub_8rh.tdf
实验5-时钟设计-最终版\db\add_sub_ish.tdf
实验5-时钟设计-最终版\db\add_sub_osh.tdf
实验5-时钟设计-最终版\db\UP3_CLOCK.(0).cnf.cdb
实验5-时钟设计-最终版\db\UP3_CLOCK.(0).cnf.hdb
实验5-时钟设计-最终版\db\UP3_CLOCK.cbx.xml
实验5-时钟设计-最终版\db\UP3_CLOCK.cmp.kpt
实验5-时钟设计-最终版\db\UP3_CLOCK.dbp
实验5-时钟设计-最终版\db\UP3_CLOCK.db_info
实验5-时钟设计-最终版\db\UP3_CLOCK.eds_overflow
实验5-时钟设计-最终版\db\UP3_CLOCK.fnsim.hdb
实验5-时钟设计-最终版\db\UP3_CLOCK.fnsim.qmsg
实验5-时钟设计-最终版\db\UP3_CLOCK.hier_info
实验5-时钟设计-最终版\db\UP3_CLOCK.hif
实验5-时钟设计-最终版\db\UP3_CLOCK.psp
实验5-时钟设计-最终版\db\UP3_CLOCK.rpp.qmsg
实验5-时钟设计-最终版\db\UP3_CLOCK.sgate.rvd
实验5-时钟设计-最终版\db\UP3_CLOCK.sgate_sm.rvd
实验5-时钟设计-最终版\db\UP3_CLOCK.sim.hdb
实验5-时钟设计-最终版\db\UP3_CLOCK.sim.qmsg
实验5-时钟设计-最终版\db\UP3_CLOCK.sim.rdb
实验5-时钟设计-最终版\db\UP3_CLOCK.sim_ori.vwf
实验5-时钟设计-最终版\db\UP3_CLOCK.syn_hier_info
实验5-时钟设计-最终版\db\wed.zsf
实验5-时钟设计-最终版\db\UP3_CLOCK.map.qmsg
实验5-时钟设计-最终版\db\UP3_CLOCK.rtlv_sg.cdb
实验5-时钟设计-最终版\db\UP3_CLOCK.rtlv.hdb
实验5-时钟设计-最终版\db\UP3_CLOCK.rtlv_sg_swap.cdb
实验5-时钟设计-最终版\db\UP3_CLOCK.pre_map.hdb
实验5-时钟设计-最终版\db\UP3_CLOCK.pre_map.cdb
实验5-时钟设计-最终版\db\UP3_CLOCK.smp_dump.txt
实验5-时钟设计-最终版\db\UP3_CLOCK.map.logdb
实验5-时钟设计-最终版\db\UP3_CLOCK.sgdiff.cdb
实验5-时钟设计-最终版\db\UP3_CLOCK.sgdiff.hdb
实验5-时钟设计-最终版\db\UP3_CLOCK.sld_design_entry_dsc.sci
实验5-时钟设计-最终版\db\UP3_CLOCK.map.cdb
实验5-时钟设计-最终版\db\UP3_CLOCK.map.hdb
实验5-时钟设计-最终版\db\UP3_CLOCK.fit.qmsg
实验5-时钟设计-最终版\db\UP3_CLOCK.cmp.logdb
实验5-时钟设计-最终版\db\UP3_CLOCK.asm.qmsg
实验5-时钟设计-最终版\db\UP3_CLOCK.tan.qmsg
实验5-时钟设计-最终版\db\UP3_CLOCK.cmp.tdb
实验5-时钟设计-最终版\db\UP3_CLOCK.cmp0.ddb
实验5-时钟设计-最终版\db\UP3_CLOCK.cmp.cdb
实验5-时钟设计-最终版\db\UP3_CLOCK.signalprobe.cdb
实验5-时钟设计-最终版\db\UP3_CLOCK.cmp.hdb
实验5-时钟设计-最终版\db\UP3_CLOCK.cmp.rdb
实验5-时钟设计-最终版\db\UP3_CLOCK.sld_design_entry.sci
实验5-时钟设计-最终版\db\UP3_CLOCK.eco.cdb
实验5-时钟设计-最终版\db
实验5-时钟设计-最终版

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．