Packet : 297821740522.rar filelist
0522\dds\_ngo\netlist.lst
0522\dds\_ngo
0522\dds\dds.bld
0522\dds\dds.ngd
0522\dds\dds_prev_built.ngd
0522\dds\dds.ise
0522\dds\dds_map.mrp
0522\dds\dds_map.map
0522\dds\dds_map.ngm
0522\dds\dds.pcf
0522\dds\dds_map.ncd
0522\dds\dds_usage.xml
0522\dds\dds.par
0522\dds\_xmsgs\xst.xmsgs
0522\dds\_xmsgs\ngdbuild.xmsgs
0522\dds\_xmsgs\map.xmsgs
0522\dds\_xmsgs\par.xmsgs
0522\dds\_xmsgs\trce.xmsgs
0522\dds\_xmsgs\bitgen.xmsgs
0522\dds\_xmsgs
0522\dds\dds.ise_ISE_Backup
0522\dds\dds_summary.xml
0522\dds\dds.ncd
0522\dds\dds.xpi
0522\dds\dds_pad.csv
0522\dds\dds.pad
0522\dds\dds_pad.txt
0522\dds\dds.unroutes
0522\dds\dds_guide.ncd
0522\dds\dds.twx
0522\dds\dds.twr
0522\dds\dds.ut
0522\dds\dds.bgn
0522\dds\dds.drc
0522\dds\dds.bit
0522\dds\device_usage_statistics.html
0522\dds\dds.ucf
0522\dds\dds.lfp
0522\dds\_pace.ucf
0522\dds\dds.cel
0522\dds\_impact.cmd
0522\dds\_impact.log
0522\dds\testdds.v
0522\dds\acc.v
0522\dds\acctochange.v
0522\dds\addchange.v
0522\dds\dds.v
0522\dds\delta.v
0522\dds\delta_convertor.v
0522\dds\delta_d.v
0522\dds\delta_data_convertor.v
0522\dds\mux2to1.v
0522\dds\mux4to1.v
0522\dds\myself_rec.v
0522\dds\phaseadd.v
0522\dds\ramp_convertor.v
0522\dds\ramp_d.v
0522\dds\ramp_data_convertor.v
0522\dds\sine.v
0522\dds\sine_convertor.v
0522\dds\sine_data_convertor.v
0522\dds\dds_summary.html
0522\dds\ramp.v
0522\dds\tmp\_cg
0522\dds\tmp
0522\dds\sine_rom.mif
0522\dds\sine_rom.vhd
0522\dds\sine_rom.vho
0522\dds\sine_rom.v
0522\dds\sine_rom.veo
0522\dds\sine_rom.asy
0522\dds\sine_rom.sym
0522\dds\sine_rom.ngc
0522\dds\sine_rom.xco
0522\dds\sine_rom_xmdf.tcl
0522\dds\sine_rom_flist.txt
0522\dds\sine_rom_readme.txt
0522\dds\templates\coregen.xml
0522\dds\templates
0522\dds\square.v
0522\dds\delta_rom.mif
0522\dds\delta_rom.vhd
0522\dds\delta_rom.vho
0522\dds\delta_rom.v
0522\dds\delta_rom.veo
0522\dds\delta_rom.asy
0522\dds\delta_rom.sym
0522\dds\delta_rom.ngc
0522\dds\delta_rom.xco
0522\dds\delta_rom_xmdf.tcl
0522\dds\delta_rom_flist.txt
0522\dds\delta_rom_readme.txt
0522\dds\ramp_rom.mif
0522\dds\ramp_rom.vhd
0522\dds\ramp_rom.vho
0522\dds\ramp_rom.v
0522\dds\ramp_rom.veo
0522\dds\ramp_rom.asy
0522\dds\ramp_rom.sym
0522\dds\ramp_rom.ngc
0522\dds\ramp_rom.xco
0522\dds\ramp_rom_xmdf.tcl
0522\dds\ramp_rom_flist.txt
0522\dds\ramp_rom_readme.txt
0522\dds\testdds_v.udo
0522\dds\testdds_v.fdo
0522\dds\transcript
0522\dds\work\_info
0522\dds\work\_temp
0522\dds\work\sine_rom\_primary.vhd
0522\dds\work\sine_rom\verilog.asm
0522\dds\work\sine_rom\_primary.dat
0522\dds\work\sine_rom
0522\dds\work\sine_data_convertor\_primary.vhd
0522\dds\work\sine_data_convertor\verilog.asm
0522\dds\work\sine_data_convertor\_primary.dat
0522\dds\work\sine_data_convertor
0522\dds\work\sine_convertor\_primary.vhd
0522\dds\work\sine_convertor\verilog.asm
0522\dds\work\sine_convertor\_primary.dat
0522\dds\work\sine_convertor
0522\dds\work\ramp_rom\_primary.vhd
0522\dds\work\ramp_rom\verilog.asm
0522\dds\work\ramp_rom\_primary.dat
0522\dds\work\ramp_rom
0522\dds\work\ramp_data_convertor\_primary.vhd
0522\dds\work\ramp_data_convertor\verilog.asm
0522\dds\work\ramp_data_convertor\_primary.dat
0522\dds\work\ramp_data_convertor
0522\dds\work\ramp_d\_primary.vhd
0522\dds\work\ramp_d\verilog.asm
0522\dds\work\ramp_d\_primary.dat
0522\dds\work\ramp_d
0522\dds\work\ramp_convertor\_primary.vhd
0522\dds\work\ramp_convertor\verilog.asm
0522\dds\work\ramp_convertor\_primary.dat
0522\dds\work\ramp_convertor
0522\dds\work\phaseadd\_primary.vhd
0522\dds\work\phaseadd\verilog.asm
0522\dds\work\phaseadd\_primary.dat
0522\dds\work\phaseadd
0522\dds\work\mux2to1\_primary.vhd
0522\dds\work\mux2to1\verilog.asm
0522\dds\work\mux2to1\_primary.dat
0522\dds\work\mux2to1
0522\dds\work\delta_rom\_primary.vhd
0522\dds\work\delta_rom\verilog.asm
0522\dds\work\delta_rom\_primary.dat
0522\dds\work\delta_rom
0522\dds\work\delta_data_convertor\_primary.vhd
0522\dds\work\delta_data_convertor\verilog.asm
0522\dds\work\delta_data_convertor\_primary.dat
0522\dds\work\delta_data_convertor
0522\dds\work\delta_d\_primary.vhd
0522\dds\work\delta_d\verilog.asm
0522\dds\work\delta_d\_primary.dat
0522\dds\work\delta_d
0522\dds\work\delta_convertor\_primary.vhd
0522\dds\work\delta_convertor\verilog.asm
0522\dds\work\delta_convertor\_primary.dat
0522\dds\work\delta_convertor
0522\dds\work\addchange\_primary.vhd
0522\dds\work\addchange\verilog.asm
0522\dds\work\addchange\_primary.dat
0522\dds\work\addchange
0522\dds\work\acc\_primary.vhd
0522\dds\work\acc\verilog.asm
0522\dds\work\acc\_primary.dat
0522\dds\work\acc
0522\dds\work\square\_primary.vhd
0522\dds\work\square\verilog.asm
0522\dds\work\square\_primary.dat
0522\dds\work\square
0522\dds\work\sine\_primary.vhd
0522\dds\work\sine\verilog.asm
0522\dds\work\sine\_primary.dat
0522\dds\work\sine
0522\dds\work\ramp\_primary.vhd
0522\dds\work\ramp\verilog.asm
0522\dds\work\ramp\_primary.dat
0522\dds\work\ramp
0522\dds\work\myself_rec\_primary.vhd
0522\dds\work\myself_rec\verilog.asm
0522\dds\work\myself_rec\_primary.dat
0522\dds\work\myself_rec
0522\dds\work\mux4to1\_primary.vhd
0522\dds\work\mux4to1\verilog.asm
0522\dds\work\mux4to1\_primary.dat
0522\dds\work\mux4to1
0522\dds\work\delta\_primary.vhd
0522\dds\work\delta\verilog.asm
0522\dds\work\delta\_primary.dat
0522\dds\work\delta
0522\dds\work\acctochange\_primary.vhd
0522\dds\work\acctochange\verilog.asm
0522\dds\work\acctochange\_primary.dat
0522\dds\work\acctochange
0522\dds\work\dds\_primary.vhd
0522\dds\work\dds\verilog.asm
0522\dds\work\dds\_primary.dat
0522\dds\work\dds
0522\dds\work\testdds_v\_primary.vhd
0522\dds\work\testdds_v\verilog.asm
0522\dds\work\testdds_v\_primary.dat
0522\dds\work\testdds_v
0522\dds\work\glbl\_primary.vhd
0522\dds\work\glbl\verilog.asm
0522\dds\work\glbl\_primary.dat
0522\dds\work\glbl
0522\dds\work
0522\dds\vsim.wlf
0522\dds\dds.prj
0522\dds\xst\projnav.tmp
0522\dds\xst\work\vlg60\sine__rom.bin
0522\dds\xst\work\vlg60
0522\dds\xst\work\vlg2D\sine__data__convertor.bin
0522\dds\xst\work\vlg2D
0522\dds\xst\work\vlg58\sine__convertor.bin
0522\dds\xst\work\vlg58
0522\dds\xst\work\vlg11\ramp__rom.bin
0522\dds\xst\work\vlg11\ramp__convertor.bin
0522\dds\xst\work\vlg11
0522\dds\xst\work\vlg7A\ramp__data__convertor.bin
0522\dds\xst\work\vlg7A
0522\dds\xst\work\vlg53\ramp__d.bin
0522\dds\xst\work\vlg53
0522\dds\xst\work\vlg52\phaseadd.bin
0522\dds\xst\work\vlg52
0522\dds\xst\work\vlg20\mux2to1.bin
0522\dds\xst\work\vlg20\acctochange.bin
0522\dds\xst\work\vlg20
0522\dds\xst\work\vlg63\delta__rom.bin
0522\dds\xst\work\vlg63
0522\dds\xst\work\vlg44\delta__data__convertor.bin
0522\dds\xst\work\vlg44
0522\dds\xst\work\vlg75\delta__d.bin
0522\dds\xst\work\vlg75
0522\dds\xst\work\vlg73\delta__convertor.bin
0522\dds\xst\work\vlg73\sine.bin
0522\dds\xst\work\vlg73
0522\dds\xst\work\vlg43\addchange.bin
0522\dds\xst\work\vlg43
0522\dds\xst\work\vlg4B\acc.bin
0522\dds\xst\work\vlg4B
0522\dds\xst\work\vlg69\square.bin
0522\dds\xst\work\vlg69
0522\dds\xst\work\vlg34\ramp.bin
0522\dds\xst\work\vlg34
0522\dds\xst\work\vlg61\myself__rec.bin
0522\dds\xst\work\vlg61
0522\dds\xst\work\vlg1A\mux4to1.bin
0522\dds\xst\work\vlg1A
0522\dds\xst\work\vlg26\delta.bin
0522\dds\xst\work\vlg26
0522\dds\xst\work\vlg2B\dds.bin
0522\dds\xst\work\vlg2B
0522\dds\xst\work\hdllib.ref
0522\dds\xst\work
0522\dds\xst\dump.xst\dds.prj\ngx\opt
0522\dds\xst\dump.xst\dds.prj\ngx\notopt
0522\dds\xst\dump.xst\dds.prj\ngx
0522\dds\xst\dump.xst\dds.prj\ntrc.scr
0522\dds\xst\dump.xst\dds.prj
0522\dds\xst\dump.xst
0522\dds\xst
0522\dds\dds.xst
0522\dds\dds.cmd_log
0522\dds\dds.syr
0522\dds\dds.lso
0522\dds\dds.ntrc_log
0522\dds\dds.ngr
0522\dds\dds.ngc
0522\dds\dds.stx
0522\dds
0522

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