To Quatus Ⅱ as a platform, the use of VHDL language digital code lock function, you can realize simulation.

Packet : 5956489lock.rar filelist
LOCK\Chain1.cdf
LOCK\cmp_state.ini
LOCK\lock.asm.rpt
LOCK\lock.done
LOCK\lock.fit.eqn
LOCK\lock.fit.rpt
LOCK\lock.fit.summary
LOCK\lock.flow.rpt
LOCK\lock.map.eqn
LOCK\lock.map.rpt
LOCK\lock.map.summary
LOCK\LOCK.PIN
LOCK\LOCK.POF
LOCK\LOCK.QPF
LOCK\LOCK.QSF
LOCK\LOCK.QWS
LOCK\LOCK.SOF
LOCK\lock.tan.rpt
LOCK\lock.tan.summary
LOCK\LOCK.VHD
LOCK\LOCK.VWF
LOCK\DB\lock.(0).cnf.cdb
LOCK\DB\lock.(0).cnf.hdb
LOCK\DB\lock.asm.qmsg
LOCK\DB\lock.asm_labs.ddb
LOCK\DB\lock.cbx.xml
LOCK\DB\lock.cmp.cdb
LOCK\DB\lock.cmp.hdb
LOCK\DB\lock.cmp.logdb
LOCK\DB\lock.cmp.rdb
LOCK\DB\lock.cmp.tdb
LOCK\DB\lock.cmp0.ddb
LOCK\DB\lock.db_info
LOCK\DB\lock.eco.cdb
LOCK\DB\lock.fit.qmsg
LOCK\DB\lock.hier_info
LOCK\DB\LOCK.HIF
LOCK\DB\lock.map.cdb
LOCK\DB\lock.map.hdb
LOCK\DB\lock.map.logdb
LOCK\DB\lock.map.qmsg
LOCK\DB\lock.pre_map.cdb
LOCK\DB\lock.pre_map.hdb
LOCK\DB\LOCK.PSP
LOCK\DB\lock.rtlv.hdb
LOCK\DB\lock.rtlv_sg.cdb
LOCK\DB\lock.rtlv_sg_swap.cdb
LOCK\DB\lock.sgdiff.cdb
LOCK\DB\lock.sgdiff.hdb
LOCK\DB\lock.signalprobe.cdb
LOCK\DB\lock.sld_design_entry.sci
LOCK\DB\lock.sld_design_entry_dsc.sci
LOCK\DB\lock.syn_hier_info
LOCK\DB\lock.tan.qmsg
LOCK\DB\lock_cmp.qrpt
LOCK\DB
LOCK

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