Introduction - If you have any usage issues, please Google them yourself
With regard to the various basic modules Verilog source code, such as adders, registers, selectors and the various test file
Packet : 105230343programe.rar filelist
程序\add.v
程序\addtest.v
程序\alladd.v
程序\alladdtest.v
程序\ALU.v
程序\ALUtest.v
程序\control.v
程序\controltest.v
程序\datapath.v
程序\decoder.v
程序\decodertest.v
程序\dff.v
程序\dfftest.v
程序\ir.v
程序\irtest.v
程序\memory.v
程序\memorytest.v
程序\mux21_32.v
程序\mux21_32test.v
程序\mux21_5.v
程序\mux21_5test.v
程序\mux41_32.v
程序\mux41_32test.v
程序\mux_32.v
程序\mux_32test.v
程序\pc.v
程序\pctest.v
程序\register.v
程序\registerfile.v
程序\registerfiletest.v
程序\registertest.v
程序\TOP.v
程序\TOP_test.v
程序\transcript
程序\zerostore.v
程序