Packet : 49636973uart(verilog).rar filelist
uart 源码 (Verilog)
uart 源码 (Verilog)\address_decode.v
uart 源码 (Verilog)\clock_divider.v
uart 源码 (Verilog)\control_operation.v
uart 源码 (Verilog)\cpu_interface.v
uart 源码 (Verilog)\serial_interface.v
uart 源码 (Verilog)\status_registers.v
uart 源码 (Verilog)\tester.v
uart 源码 (Verilog)\transcript
uart 源码 (Verilog)\uart_tb.v
uart 源码 (Verilog)\uart_top.v
uart 源码 (Verilog)\xmit_rcv_control.v

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