Introduction - If you have any usage issues, please Google them yourself
Using 0.18um standard CMOS process design, embedded ASIX CORE (32 bit RISC core, compatible with ARM720T, with 8KB Data Cache directives and full-featured MMU), the use of the structure of von Neumann
Packet : 75448170sep4020.rar filelist
SEP4020用户手册.pdf