The sine wave generator based on FPGA design, have a certain reference value, a more detailed written

Packet : 43680537sin.rar filelist
sin\adder10b.vhd
sin\adder32b.vhd
sin\and2.vhd
sin\and2ab.vhd
sin\cmp_state.ini
sin\db\altsyncram_2q92.tdf
sin\db\altsyncram_40u.tdf
sin\db\altsyncram_cvr.tdf
sin\db\altsyncram_eui2.tdf
sin\db\altsyncram_o351.tdf
sin\db\altsyncram_qqb2.tdf
sin\db\cntr_8b8.tdf
sin\db\cntr_pd8.tdf
sin\db\dds_vhdl.(0).cnf.cdb
sin\db\dds_vhdl.(0).cnf.hdb
sin\db\dds_vhdl.(1).cnf.cdb
sin\db\dds_vhdl.(1).cnf.hdb
sin\db\dds_vhdl.(10).cnf.cdb
sin\db\dds_vhdl.(10).cnf.hdb
sin\db\dds_vhdl.(11).cnf.cdb
sin\db\dds_vhdl.(11).cnf.hdb
sin\db\dds_vhdl.(12).cnf.cdb
sin\db\dds_vhdl.(12).cnf.hdb
sin\db\dds_vhdl.(13).cnf.cdb
sin\db\dds_vhdl.(13).cnf.hdb
sin\db\dds_vhdl.(14).cnf.cdb
sin\db\dds_vhdl.(14).cnf.hdb
sin\db\dds_vhdl.(15).cnf.cdb
sin\db\dds_vhdl.(15).cnf.hdb
sin\db\dds_vhdl.(16).cnf.cdb
sin\db\dds_vhdl.(16).cnf.hdb
sin\db\dds_vhdl.(17).cnf.cdb
sin\db\dds_vhdl.(17).cnf.hdb
sin\db\dds_vhdl.(18).cnf.cdb
sin\db\dds_vhdl.(18).cnf.hdb
sin\db\dds_vhdl.(19).cnf.cdb
sin\db\dds_vhdl.(19).cnf.hdb
sin\db\dds_vhdl.(2).cnf.cdb
sin\db\dds_vhdl.(2).cnf.hdb
sin\db\dds_vhdl.(20).cnf.cdb
sin\db\dds_vhdl.(20).cnf.hdb
sin\db\dds_vhdl.(21).cnf.cdb
sin\db\dds_vhdl.(21).cnf.hdb
sin\db\dds_vhdl.(22).cnf.cdb
sin\db\dds_vhdl.(22).cnf.hdb
sin\db\dds_vhdl.(3).cnf.cdb
sin\db\dds_vhdl.(3).cnf.hdb
sin\db\dds_vhdl.(4).cnf.cdb
sin\db\dds_vhdl.(4).cnf.hdb
sin\db\dds_vhdl.(5).cnf.cdb
sin\db\dds_vhdl.(5).cnf.hdb
sin\db\dds_vhdl.(6).cnf.cdb
sin\db\dds_vhdl.(6).cnf.hdb
sin\db\dds_vhdl.(7).cnf.cdb
sin\db\dds_vhdl.(7).cnf.hdb
sin\db\dds_vhdl.(8).cnf.cdb
sin\db\dds_vhdl.(8).cnf.hdb
sin\db\dds_vhdl.(9).cnf.cdb
sin\db\dds_vhdl.(9).cnf.hdb
sin\db\dds_vhdl.asm.qmsg
sin\db\dds_vhdl.cbx.xml
sin\db\dds_vhdl.cmp.cdb
sin\db\dds_vhdl.cmp.hdb
sin\db\dds_vhdl.cmp.kpt
sin\db\dds_vhdl.cmp.logdb
sin\db\dds_vhdl.cmp.rdb
sin\db\dds_vhdl.cmp.tdb
sin\db\dds_vhdl.cmp0.ddb
sin\db\dds_vhdl.dbp
sin\db\dds_vhdl.db_info
sin\db\dds_vhdl.eco.cdb
sin\db\dds_vhdl.fit.qmsg
sin\db\dds_vhdl.hier_info
sin\db\dds_vhdl.hif
sin\db\dds_vhdl.map.cdb
sin\db\dds_vhdl.map.hdb
sin\db\dds_vhdl.map.logdb
sin\db\dds_vhdl.map.qmsg
sin\db\dds_vhdl.pre_map.cdb
sin\db\dds_vhdl.pre_map.hdb
sin\db\dds_vhdl.psp
sin\db\dds_vhdl.rpp.qmsg
sin\db\dds_vhdl.rtlv.hdb
sin\db\dds_vhdl.rtlv_sg.cdb
sin\db\dds_vhdl.rtlv_sg_swap.cdb
sin\db\dds_vhdl.sgate.rvd
sin\db\dds_vhdl.sgate_sm.rvd
sin\db\dds_vhdl.sgdiff.cdb
sin\db\dds_vhdl.sgdiff.hdb
sin\db\dds_vhdl.signalprobe.cdb
sin\db\dds_vhdl.sld_design_entry.sci
sin\db\dds_vhdl.sld_design_entry_dsc.sci
sin\db\dds_vhdl.syn_hier_info
sin\db\dds_vhdl.tan.qmsg
sin\db\dds_vhdl_cmp.qrpt
sin\db\dds_vhdl_sim.qrpt
sin\db\decode_9ie.tdf
sin\db\decode_ogi.tdf
sin\db\wed.zsf
sin\dds_vhdl.asm.rpt
sin\dds_vhdl.done
sin\dds_vhdl.fit.eqn
sin\dds_vhdl.fit.rpt
sin\dds_vhdl.fit.smsg
sin\dds_vhdl.fit.summary
sin\dds_vhdl.flow.rpt
sin\dds_vhdl.map.eqn
sin\dds_vhdl.map.rpt
sin\dds_vhdl.map.summary
sin\dds_vhdl.pin
sin\dds_vhdl.pof
sin\dds_vhdl.qpf
sin\dds_vhdl.qsf
sin\dds_vhdl.qws
sin\dds_vhdl.sim.rpt
sin\dds_vhdl.sof
sin\dds_vhdl.tan.rpt
sin\dds_vhdl.tan.summary
sin\dds_vhdl.vhd
sin\dds_vhdl.vwf
sin\dds_vhdl_assignment_defaults.qdf
sin\pll1.bsf
sin\pll1.cmp
sin\pll1.vhd
sin\reg10b.vhd
sin\reg32b.vhd
sin\romd.mif
sin\sim.cfg
sin\sin_rom.bsf
sin\sin_rom.cmp
sin\sin_rom.vhd
sin\正弦波采样数据.txt
sin\db
sin

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．