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dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
Packet : 105230315clock.rar filelist
clock
clock\automake.log
clock\clock.bld
clock\clock.gyd
clock\clock.jed
clock\clock.jhd
clock\clock.jid
clock\clock.mfd
clock\clock.ngc
clock\clock.ngd
clock\clock.npl
clock\clock.pnx
clock\clock.prj
clock\clock.ptf
clock\clock.rpt
clock\clock.syr
clock\clock.ucf
clock\clock.v
clock\clock.vm6
clock\clock.xst
clock\clock_ngdbuild.nav
clock\clock._prj
clock\last_used.ucf
clock\ngdbuild.rsp
clock\tmperr.err
clock\_chipview.tcl
clock\_cpldfit.rsp
clock\_cpldfit.tcl
clock\_impact.log
clock\_ngdbld.rsp
clock\__clock_2prj_exewrap.rsp
clock\__impact.rsp
clock\__projnav.log
clock\_ngo
clock\_ngo\netlist.lst